Simulation time control in VHDL

Introduction

Simulation time control helps you decide when things happen in your VHDL testbench. It lets you wait, delay, or move forward in time to see how your design behaves.

When you want to wait a specific time before checking a signal.

When you need to apply inputs to your design at certain moments.

When you want to simulate clock cycles by waiting fixed time intervals.

When you want to pause simulation to observe outputs.

When you want to end simulation after a certain time.

Syntax

VHDL

wait for <time_expression>;
-- or
wait until <condition>;
-- or
wait on <signal_list>;

wait for pauses simulation for a set time.

wait until pauses until a condition is true.

wait on pauses until one of the signals in the list changes.

Examples

Pause simulation for 10 nanoseconds.

VHDL

wait for 10 ns;

Pause simulation until the clock signal is high.

VHDL

wait until clk = '1';

Pause simulation until the reset signal changes.

VHDL

wait on reset;

Sample Program

This testbench creates a clock that toggles every 5 ns using wait for. The test process waits 20 ns, then waits until the clock is high, reports messages, and finishes.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture sim of testbench is
  signal clk : std_logic := '0';
begin
  -- Clock process: toggles every 5 ns
  clk_process : process
  begin
    clk <= '0';
    wait for 5 ns;
    clk <= '1';
    wait for 5 ns;
  end process;

  -- Test process
  test_process : process
  begin
    wait for 20 ns; -- wait 20 ns before starting
    report "Starting test at 20 ns";
    wait until clk = '1'; -- wait for clock high
    report "Clock is high";
    wait for 10 ns;
    report "Test finished";
    wait;
  end process;
end sim;

Important Notes

Use wait; to pause forever at the end of a testbench process.

Simulation time units like ns (nanoseconds) must match your design's time scale.

Reports help you see when events happen during simulation.

Summary

Simulation time control lets you pause or wait in your testbench.

Use wait for to delay a fixed time, wait until for a condition, and wait on for signal changes.

This helps test your design step-by-step and see how it reacts over time.

Practice

1. What does the VHDL statement wait for 10 ns; do in a testbench?

easy

A. Pauses the simulation for 10 nanoseconds before continuing.

B. Waits until a signal changes value.

C. Waits until a condition becomes true.

D. Ends the simulation immediately.

Solution

1. Step 1: Understand the wait for statement

   The wait for statement pauses the simulation for a fixed amount of time.

2. Step 2: Apply to the given time

   Here, it pauses for 10 nanoseconds before continuing the simulation.

3. Final Answer:

   Pauses the simulation for 10 nanoseconds before continuing. -> Option A

4. Quick Check:

   wait for 10 ns; = Pause 10 ns [OK]

Hint: Remember: 'wait for' pauses fixed time, not conditions. [OK]

Common Mistakes:

• Confusing 'wait for' with 'wait until' or 'wait on'.
• Thinking it waits for a signal change.
• Assuming it ends simulation.

2. Which of the following is the correct syntax to wait until signal clk becomes '1' in VHDL?

easy

A. wait for clk = '1';

B. wait on clk = '1';

C. wait until clk = '1';

D. wait clk = '1';

Solution

1. Step 1: Identify correct wait syntax for condition

   The correct syntax to wait for a condition is wait until condition;.

2. Step 2: Apply to signal clk equals '1'

   So, wait until clk = '1'; waits until clk becomes '1'.

3. Final Answer:

   wait until clk = '1'; -> Option C

4. Quick Check:

   Condition wait = wait until [OK]

Hint: Use 'wait until' for conditions, not 'wait for' or 'wait on'. [OK]

Common Mistakes:

• Using 'wait for' with a condition instead of time.
• Using 'wait on' incorrectly with a condition.
• Omitting 'until' keyword.

3. Consider the following VHDL testbench snippet:

signal clk : std_logic := '0';
begin
  clk_process: process
  begin
    clk <= '0';
    wait for 5 ns;
    clk <= '1';
    wait for 5 ns;
  end process;

What is the total time for one full clock cycle of clk?

medium

A. 5 ns

B. 15 ns

C. 20 ns

D. 10 ns

Solution

1. Step 1: Analyze the clock toggling times

   The clock is set to '0', then waits 5 ns, then set to '1', then waits 5 ns.

2. Step 2: Calculate total cycle time

   One full cycle is from '0' to '1' and back to '0', which takes 5 ns + 5 ns = 10 ns.

3. Final Answer:

   10 ns -> Option D

4. Quick Check:

   5 ns + 5 ns = 10 ns [OK]

Hint: Add all wait times between signal changes for full cycle. [OK]

Common Mistakes:

• Counting only one wait period.
• Confusing signal assignments with wait times.
• Ignoring that both waits add up.

4. Identify the error in this VHDL wait statement:

wait until clk = 1;

medium

A. Missing semicolon at the end.

B. Signal value should be in single quotes: '1'.

C. Cannot use 'wait until' with signals.

D. The statement should be 'wait for clk = 1;'.

Solution

1. Step 1: Check signal value syntax

   In VHDL, std_logic values must be in single quotes, e.g., '1', not 1.

2. Step 2: Confirm correct usage of 'wait until'

   The syntax wait until clk = '1'; is correct; only the quotes are missing.

3. Final Answer:

   Signal value should be in single quotes: '1'. -> Option B

4. Quick Check:

   std_logic values need single quotes [OK]

Hint: Use single quotes for std_logic values in conditions. [OK]

Common Mistakes:

• Using numeric 1 instead of character '1'.
• Confusing 'wait until' with 'wait for'.
• Omitting semicolon (though not the main error here).

5. You want to create a testbench process that waits for a signal ready to become '1', then waits an additional 20 ns before starting the next operation. Which sequence of wait statements correctly achieves this?

hard

A. wait until ready = '1'; wait for 20 ns;

B. wait for 20 ns; wait until ready = '1';

C. wait on ready; wait for 20 ns;

D. wait until ready = 1 and wait for 20 ns;

Solution

1. Step 1: Wait for the signal ready to become '1'

   The correct syntax is wait until ready = '1'; to pause until the signal is '1'.

2. Step 2: Wait an additional fixed time

   After the signal is '1', use wait for 20 ns; to delay 20 nanoseconds before continuing.

3. Final Answer:

   wait until ready = '1'; wait for 20 ns; -> Option A

4. Quick Check:

   Condition wait then fixed wait = wait until ready = '1'; wait for 20 ns; [OK]

Hint: Wait for condition first, then fixed delay. [OK]

Common Mistakes:

• Reversing the order of waits.
• Using 'wait on' without condition.
• Missing single quotes around '1'.