Simulation time control in VHDL

Introduction

Simulation time control helps you decide when things happen in your VHDL testbench. It lets you wait, delay, or move forward in time to see how your design behaves.

When you want to wait a specific time before checking a signal.

When you need to apply inputs to your design at certain moments.

When you want to simulate clock cycles by waiting fixed time intervals.

When you want to pause simulation to observe outputs.

When you want to end simulation after a certain time.

Syntax

VHDL

wait for <time_expression>;
-- or
wait until <condition>;
-- or
wait on <signal_list>;

wait for pauses simulation for a set time.

wait until pauses until a condition is true.

wait on pauses until one of the signals in the list changes.

Examples

Pause simulation for 10 nanoseconds.

VHDL

wait for 10 ns;

Pause simulation until the clock signal is high.

VHDL

wait until clk = '1';

Pause simulation until the reset signal changes.

VHDL

wait on reset;

Sample Program

This testbench creates a clock that toggles every 5 ns using wait for. The test process waits 20 ns, then waits until the clock is high, reports messages, and finishes.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture sim of testbench is
  signal clk : std_logic := '0';
begin
  -- Clock process: toggles every 5 ns
  clk_process : process
  begin
    clk <= '0';
    wait for 5 ns;
    clk <= '1';
    wait for 5 ns;
  end process;

  -- Test process
  test_process : process
  begin
    wait for 20 ns; -- wait 20 ns before starting
    report "Starting test at 20 ns";
    wait until clk = '1'; -- wait for clock high
    report "Clock is high";
    wait for 10 ns;
    report "Test finished";
    wait;
  end process;
end sim;

Important Notes

Use wait; to pause forever at the end of a testbench process.

Simulation time units like ns (nanoseconds) must match your design's time scale.

Reports help you see when events happen during simulation.

Summary

Simulation time control lets you pause or wait in your testbench.

Use wait for to delay a fixed time, wait until for a condition, and wait on for signal changes.

This helps test your design step-by-step and see how it reacts over time.