Assert statement for verification in VHDL

Introduction

The assert statement helps check if your VHDL code works correctly by testing conditions during simulation. It tells you if something is wrong.

To check if a signal has the expected value during simulation.

To verify timing conditions in your design.

To catch unexpected states or errors early in simulation.

To document assumptions or requirements in your code.

To stop simulation when a critical error occurs.

Syntax

VHDL

assert condition
  report "message"
  severity level;

condition is what you want to check (true or false).

message is shown if the condition is false.

severity can be NOTE, WARNING, ERROR, or FAILURE.

Examples

Checks if signal a is '1'. If not, it shows the message.

VHDL

assert a = '1'
  report "Signal a is not 1";

Checks if count is less than 10. If false, shows error message and severity ERROR.

VHDL

assert count < 10
  report "Count exceeded limit" severity ERROR;

Warns if reset is not '0', but simulation continues.

VHDL

assert reset = '0'
  report "Reset should be low" severity WARNING;

Sample Program

This simple test sets signal a to '0' and then checks if it is '1'. The assert will fail and report an error during simulation.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity test_assert is
end test_assert;

architecture behavior of test_assert is
  signal a : std_logic := '0';
begin
  process
  begin
    a <= '0';
    wait for 10 ns;
    assert a = '1'
      report "Signal a is not 1" severity ERROR;
    wait;
  end process;
end behavior;

Important Notes

Assert statements only work during simulation, not in actual hardware.

Severity levels help control how serious the problem is.

You can use assert to stop simulation on critical errors with severity FAILURE or ERROR.

Summary

Assert checks conditions during simulation to find errors early.

Use assert with a condition, message, and severity level.

It helps verify your design works as expected before building hardware.