Signal assignment operator in VHDL

Introduction

The signal assignment operator in VHDL is used to change the value of a signal. Signals represent wires or connections in hardware, and assigning them updates their state.

When you want to update the value of a signal inside a process or architecture.

When modeling hardware behavior that changes over time, like a flip-flop output.

When you need to connect outputs of one component to inputs of another using signals.

When describing how signals react to events or conditions in your design.

Syntax

VHDL

signal_name <= expression;

The operator used is <=, called the signal assignment operator.

Signal assignments happen after the process suspends, so changes take effect in the next simulation cycle.

Examples

Assigns the value '1' to the signal clk.

VHDL

clk <= '1';

Copies the value of data_in signal to data_out.

VHDL

data_out <= data_in;

Assigns the sum of signals a and b to sum.

VHDL

sum <= a + b;

Sample Program

This VHDL code shows how to use the signal assignment operator to update a signal temp_sum inside a process. The output sum is then assigned the value of temp_sum.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity signal_example is
  port(
    a : in std_logic;
    b : in std_logic;
    sum : out std_logic
  );
end signal_example;

architecture behavior of signal_example is
  signal temp_sum : std_logic;
begin
  process(a, b)
  begin
    temp_sum <= a or b;  -- signal assignment
  end process;

  sum <= temp_sum;  -- assign signal to output
end behavior;

Important Notes

Signal assignments use the <= operator, not the variable assignment :=.

Signal updates happen after the process finishes, so the new value is visible in the next simulation cycle.

Inside a process, use signals to model hardware wires and variables for temporary calculations.

Summary

The signal assignment operator <= updates signals in VHDL.

Signal changes take effect after the process suspends, reflecting hardware timing.

Use signals to represent hardware connections and update them with <=.