Signal vs variable vs constant in VHDL

Introduction

Signals, variables, and constants are ways to store and change data in VHDL. They help control how your digital circuit behaves.

Use a signal when you want to communicate between different parts of your circuit or between processes.

Use a variable inside a process when you need temporary storage that updates immediately.

Use a constant when you have a fixed value that does not change during simulation.

Syntax

VHDL

signal signal_name : type := initial_value;
variable variable_name : type := initial_value;
constant constant_name : type := value;

Signals are declared outside processes, variables inside processes.

Constants must be assigned a value when declared and cannot change.

Examples

This declares a signal named clk of type std_logic with initial value '0'.

VHDL

signal clk : std_logic := '0';

This declares a variable count inside a process that updates immediately when assigned.

VHDL

process
  variable count : integer := 0;
begin
  count := count + 1;
end process;

This declares a constant MAX_VALUE with a fixed value 255.

VHDL

constant MAX_VALUE : integer := 255;

Sample Program

This example shows a signal sig_a, a variable var_c, and a constant CONST_B. The signal updates after the process ends, the variable updates immediately, and the constant stays the same.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity example is
end example;

architecture behavior of example is
  signal sig_a : integer := 0;
  constant CONST_B : integer := 10;
begin
  process
    variable var_c : integer := 0;
  begin
    sig_a <= sig_a + 1;  -- signal updates after process ends
    var_c := var_c + 1;   -- variable updates immediately
    report "Signal sig_a = " & integer'image(sig_a);
    report "Variable var_c = " & integer'image(var_c);
    report "Constant CONST_B = " & integer'image(CONST_B);
    wait for 10 ns;
  end process;
end behavior;

Important Notes

Signals represent wires and update after the process finishes.

Variables are like local memory inside a process and update immediately.

Constants never change and help make your code clearer and safer.

Summary

Signals communicate between processes and update after process ends.

Variables are temporary inside processes and update immediately.

Constants hold fixed values that never change.

Practice

1. Which of the following best describes a signal in VHDL?

easy

A. It communicates between processes and updates after the process ends.

B. It holds a fixed value that never changes.

C. It is temporary and updates immediately inside a process.

D. It is used only for constants and cannot change.

Solution

1. Step 1: Understand the role of signals

   Signals are used to communicate between different processes in VHDL and their values update only after the process finishes executing.

2. Step 2: Compare with variables and constants

   Variables update immediately inside a process, and constants never change. Signals differ by updating after the process ends.

3. Final Answer:

   It communicates between processes and updates after the process ends. -> Option A

4. Quick Check:

   Signal = Communicates between processes [OK]

Hint: Signals update after process ends, variables update immediately [OK]

Common Mistakes:

• Confusing signals with variables updating immediately
• Thinking constants can change
• Assuming signals update instantly inside processes

2. Which of the following is the correct way to declare a constant in VHDL?

easy

A. variable MAX_VALUE : integer := 100;

B. signal MAX_VALUE : integer := 100;

C. const MAX_VALUE : integer := 100;

D. constant MAX_VALUE : integer := 100;

Solution

1. Step 1: Recall constant declaration syntax

   In VHDL, constants are declared using the keyword constant followed by the name, type, and value.

2. Step 2: Check each option

   constant MAX_VALUE : integer := 100; (D) uses constant correctly. A uses variable, B uses signal, and C uses an invalid keyword const.

3. Final Answer:

   constant MAX_VALUE : integer := 100; -> Option D

4. Quick Check:

   Constant declaration uses keyword 'constant' [OK]

Hint: Constants use keyword 'constant' not 'variable' or 'signal' [OK]

Common Mistakes:

• Using 'variable' or 'signal' instead of 'constant'
• Using 'const' which is not valid in VHDL
• Omitting the type or value in declaration

3. Consider the following VHDL process:

process
  variable temp : integer := 0;
  begin
    temp := temp + 1;
    output_signal <= temp;
end process;

What will be the value assigned to output_signal after the first process execution?

medium

A. 0

B. 1

C. Undefined

D. Error

Solution

1. Step 1: Understand variable and signal update timing

   The variable temp is initialized to 0 and updates immediately inside the process: temp := temp + 1; sets it to 1.

2. Step 2: Determine signal value after process

   The assignment output_signal <= temp; (temp=1) schedules the update to 1, which takes effect after the process ends. Thus, after the first execution, output_signal is 1.

3. Final Answer:

   1 -> Option B

4. Quick Check:

   Variable immediate, signal after process; output_signal = 1 [OK]

Hint: Signals update after process ends; variables update immediately [OK]

Common Mistakes:

• Thinking signal assignment schedules the old variable value (0)
• Confusing variable and signal update timing
• Expecting output_signal to remain 0 after process

4. Identify the error in the following VHDL code snippet:

process
  variable count : integer := 0;
begin
  count := count + 1;
  signal_flag <= count;
end process;

medium

A. No error; the code is correct.

B. Signals cannot be assigned inside a process.

C. Variables cannot be initialized inside a process.

D. Signal assignment uses '<=' but variable assignment uses ':='; mixing them is incorrect.

Solution

1. Step 1: Check variable declaration

   Variables can be declared and initialized in the process declarative region before begin, so C is wrong.

2. Step 2: Check assignment syntax

   Variables use :=, signals use <=; the code uses both correctly, so A (claiming mixing incorrect) is wrong.

3. Step 3: Check signal usage

   Signals must be assigned inside processes to drive them, so B is wrong.

4. Final Answer:

   No error; the code is correct. -> Option A

5. Quick Check:

   Correct syntax: decl before begin, proper operators [OK]

Hint: Remember '<=' for signals, ':=' for variables [OK]

Common Mistakes:

• Thinking variables can't be initialized inside processes
• Confusing signal and variable assignment operators
• Thinking mixing assignment operators is an error

5. You want to create a VHDL process that counts clock cycles and holds a fixed maximum count value. Which combination correctly uses signal, variable, and constant?

hard

A. Declare a signal MAX_COUNT, a constant count inside the process, and a variable output_count.

B. Declare a variable MAX_COUNT, a signal count inside the process, and a constant output_count.

C. Declare a constant MAX_COUNT, a variable count inside the process, and a signal output_count to communicate outside.

D. Declare all as variables inside the process.

Solution

1. Step 1: Understand roles of constant, variable, and signal

   The maximum count value should never change, so it must be a constant. The count that changes during process execution is best as a variable for immediate updates. The output count that communicates outside the process should be a signal.

2. Step 2: Match roles to options

   Declare a constant MAX_COUNT, a variable count inside the process, and a signal output_count to communicate outside. correctly assigns MAX_COUNT as constant, count as variable inside the process, and output_count as signal. Other options misuse these roles.

3. Final Answer:

   Declare a constant MAX_COUNT, a variable count inside the process, and a signal output_count to communicate outside. -> Option C

4. Quick Check:

   Constant fixed, variable immediate, signal communicates [OK]

Hint: Constant fixed, variable immediate, signal communicates outside [OK]

Common Mistakes:

• Using variable for fixed max count
• Using signal inside process for immediate updates
• Declaring all as variables ignoring constants and signals