Decoder and encoder design in VHDL

Introduction

A decoder changes a small input code into a bigger output with one active line. An encoder does the opposite, turning many inputs into a smaller output code.

When you want to select one device out of many using a few control signals.

When you need to convert multiple input signals into a smaller binary code.

When designing digital circuits like memory address decoding or keypad input.

When you want to simplify wiring by encoding multiple signals into fewer lines.

Syntax

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity decoder_2to4 is
  port(
    input : in std_logic_vector(1 downto 0);
    output : out std_logic_vector(3 downto 0)
  );
end decoder_2to4;

architecture behavior of decoder_2to4 is
begin
  process(input)
  begin
    output <= (others => '0');
    case input is
      when "00" => output(0) <= '1';
      when "01" => output(1) <= '1';
      when "10" => output(2) <= '1';
      when "11" => output(3) <= '1';
      when others => output <= (others => '0');
    end case;
  end process;
end behavior;

Use std_logic_vector for input and output signals representing bits.

The case statement helps select which output line to activate based on input.

Examples

This is a simple 4-to-2 encoder that converts one active input line into a 2-bit code.

VHDL

entity encoder_4to2 is
  port(
    input : in std_logic_vector(3 downto 0);
    output : out std_logic_vector(1 downto 0)
  );
end encoder_4to2;

architecture behavior of encoder_4to2 is
begin
  process(input)
  begin
    case input is
      when "0001" => output <= "00";
      when "0010" => output <= "01";
      when "0100" => output <= "10";
      when "1000" => output <= "11";
      when others => output <= "00"; -- default
    end case;
  end process;
end behavior;

This decoder activates one of eight outputs based on a 3-bit input.

VHDL

architecture behavior of decoder_3to8 is
begin
  process(input)
  begin
    output <= (others => '0');
    case input is
      when "000" => output(0) <= '1';
      when "001" => output(1) <= '1';
      when "010" => output(2) <= '1';
      when "011" => output(3) <= '1';
      when "100" => output(4) <= '1';
      when "101" => output(5) <= '1';
      when "110" => output(6) <= '1';
      when "111" => output(7) <= '1';
      when others => output <= (others => '0');
    end case;
  end process;
end behavior;

Sample Program

This program defines a 2-to-4 decoder and a testbench that cycles through all inputs. It prints the input number and the output vector showing which output line is active.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity decoder_2to4 is
  port(
    input : in std_logic_vector(1 downto 0);
    output : out std_logic_vector(3 downto 0)
  );
end decoder_2to4;

architecture behavior of decoder_2to4 is
begin
  process(input)
  begin
    output <= (others => '0');
    case input is
      when "00" => output(0) <= '1';
      when "01" => output(1) <= '1';
      when "10" => output(2) <= '1';
      when "11" => output(3) <= '1';
      when others => output <= (others => '0');
    end case;
  end process;
end behavior;

-- Testbench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_decoder is
end tb_decoder;

architecture test of tb_decoder is
  signal input : std_logic_vector(1 downto 0) := "00";
  signal output : std_logic_vector(3 downto 0);
begin
  uut: entity work.decoder_2to4
    port map(
      input => input,
      output => output
    );

  process
  begin
    for i in 0 to 3 loop
      input <= std_logic_vector(to_unsigned(i, 2));
      wait for 10 ns;
      report "Input: " & integer'image(i) & " Output: " & std_logic_vector(output).to_string;
    end loop;
    wait;
  end process;
end test;

Important Notes

Decoders usually have one active output line for each input code.

Encoders assume only one input line is active at a time to avoid confusion.

Use testbenches to verify your design by simulating different inputs.

Summary

A decoder turns a small input code into one active output line.

An encoder converts one active input line into a smaller output code.

Both are useful for selecting devices or compressing signals in digital circuits.

Practice

1.

What is the main function of a decoder in VHDL?

easy

A. It converts a binary input code into one active output line.

B. It compresses multiple output lines into a smaller input code.

C. It stores data temporarily in registers.

D. It performs arithmetic operations on input signals.

Solution

1. Step 1: Understand the role of a decoder

   A decoder takes a small binary input and activates exactly one output line corresponding to that input.

2. Step 2: Compare with other options

   Options A, B, and C describe other components or functions, not a decoder's main role.

3. Final Answer:

   It converts a binary input code into one active output line. -> Option A

4. Quick Check:

   Decoder = binary input to one active output [OK]

Hint: Decoder activates one output from input code [OK]

Common Mistakes:

• Confusing decoder with encoder
• Thinking decoder stores data
• Assuming decoder performs arithmetic

2.

Which of the following is the correct VHDL syntax to declare a 2-to-4 decoder output signal named Y as a 4-bit std_logic_vector?

easy

A. signal Y : std_logic_vector(3 downto 1);

B. signal Y : std_logic_vector(0 downto 3);

C. signal Y : std_logic_vector(3 downto 0);

D. signal Y : std_logic_vector(4 to 1);

Solution

1. Step 1: Understand std_logic_vector indexing

   In VHDL, vectors are often declared with 'downto' for descending indices, so 3 downto 0 means 4 bits indexed 3,2,1,0.

2. Step 2: Check options for correct 4-bit declaration

   signal Y : std_logic_vector(3 downto 0); uses '3 downto 0' which is standard and correct. The other options are incorrect: B '0 downto 3' (invalid direction), C '3 downto 1' (3 bits), D '4 to 1' (invalid direction).

3. Final Answer:

   signal Y : std_logic_vector(3 downto 0); -> Option C

4. Quick Check:

   4-bit vector usually declared as 3 downto 0 [OK]

Hint: Use 'downto' for descending bit order in vectors [OK]

Common Mistakes:

• Using incorrect index ranges
• Confusing 'to' and 'downto' keywords
• Declaring wrong vector size

3.

Given the following VHDL code for a 2-to-4 decoder, what is the output Y when input A = "10"?

process(A)
begin
  case A is
    when "00" => Y <= "0001";
    when "01" => Y <= "0010";
    when "10" => Y <= "0100";
    when "11" => Y <= "1000";
    when others => Y <= "0000";
  end case;
end process;

medium

A. "0100"

B. "0010"

C. "0001"

D. "1000"

Solution

1. Step 1: Match input A with case branches

   The input A is "10", so the case statement matches the third when clause: when "10" => Y <= "0100".

2. Step 2: Confirm output value

   The output Y is assigned "0100" for input "10".

3. Final Answer:

   "0100" -> Option A

4. Quick Check:

   Input "10" activates third output "0100" [OK]

Hint: Match input bits exactly in case statement [OK]

Common Mistakes:

• Mixing up binary input values
• Choosing output for wrong input
• Ignoring 'when others' clause

4.

Identify the error in this VHDL code snippet for a 4-to-2 encoder:

process(I)
begin
  if I = "0001" then Y <= "00";
  elsif I = "0010" then Y <= "01";
  elsif I = "0100" then Y <= "10";
  elsif I = "1000" then Y <= "11";
  else Y <= "00";
end if;
end process;

medium

A. Input I should be declared as std_logic_vector(3 downto 0).

B. The code does not handle multiple active inputs correctly.

C. The process sensitivity list should include Y.

D. The output Y should be declared as std_logic_vector(3 downto 0).

Solution

1. Step 1: Analyze input and output declarations

   Input I is likely a 4-bit vector representing active lines; output Y is 2 bits encoding which input is active.

2. Step 2: Check logic for multiple active inputs

   The code assumes only one input bit is active at a time. It does not handle cases where multiple bits in I are '1', which is invalid for an encoder.

3. Step 3: Review other options

   Input I should be declared as std_logic_vector(3 downto 0). is likely true but not an error in this snippet. The process sensitivity list should include Y. is incorrect; Y should not be in sensitivity list. The output Y should be declared as std_logic_vector(3 downto 0). is wrong because Y is 2 bits, not 4.

4. Final Answer:

   The code does not handle multiple active inputs correctly. -> Option B

5. Quick Check:

   Encoder needs single active input line [OK]

Hint: Encoder requires only one active input line [OK]

Common Mistakes:

• Ignoring multiple active inputs
• Incorrect sensitivity list
• Wrong output size declaration

5.

You need to design a 3-to-8 decoder in VHDL that activates one output line based on a 3-bit input A. Which of the following code snippets correctly implements this decoder?

process(A)
begin
  Y <= (others => '0');
  case A is
    when "000" => Y(0) <= '1';
    when "001" => Y(1) <= '1';
    when "010" => Y(2) <= '1';
    when "011" => Y(3) <= '1';
    when "100" => Y(4) <= '1';
    when "101" => Y(5) <= '1';
    when "110" => Y(6) <= '1';
    when "111" => Y(7) <= '1';
    when others => Y <= (others => '0');
  end case;
end process;

hard

A. The case statement syntax is invalid in VHDL.

B. The code incorrectly sets multiple outputs high simultaneously.

C. The code misses resetting outputs before setting one high.

D. This code correctly sets one output bit high and resets others to zero.

Solution

1. Step 1: Check output initialization

   The line 'Y <= (others => '0');' sets all outputs to zero before activating one output line.

2. Step 2: Verify case statement logic

   Each case sets exactly one bit of Y to '1' based on input A, which is correct for a decoder.

3. Step 3: Confirm syntax correctness

   The case statement and assignments follow proper VHDL syntax.

4. Final Answer:

   This code correctly sets one output bit high and resets others to zero. -> Option D

5. Quick Check:

   Initialize outputs then activate one line [OK]

Hint: Reset outputs before setting one active bit [OK]

Common Mistakes:

• Not resetting outputs before setting one
• Setting multiple outputs high
• Incorrect case statement syntax