Decoder and encoder design in VHDL

Introduction

A decoder changes a small input code into a bigger output with one active line. An encoder does the opposite, turning many inputs into a smaller output code.

When you want to select one device out of many using a few control signals.

When you need to convert multiple input signals into a smaller binary code.

When designing digital circuits like memory address decoding or keypad input.

When you want to simplify wiring by encoding multiple signals into fewer lines.

Syntax

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity decoder_2to4 is
  port(
    input : in std_logic_vector(1 downto 0);
    output : out std_logic_vector(3 downto 0)
  );
end decoder_2to4;

architecture behavior of decoder_2to4 is
begin
  process(input)
  begin
    output <= (others => '0');
    case input is
      when "00" => output(0) <= '1';
      when "01" => output(1) <= '1';
      when "10" => output(2) <= '1';
      when "11" => output(3) <= '1';
      when others => output <= (others => '0');
    end case;
  end process;
end behavior;

Use std_logic_vector for input and output signals representing bits.

The case statement helps select which output line to activate based on input.

Examples

This is a simple 4-to-2 encoder that converts one active input line into a 2-bit code.

VHDL

entity encoder_4to2 is
  port(
    input : in std_logic_vector(3 downto 0);
    output : out std_logic_vector(1 downto 0)
  );
end encoder_4to2;

architecture behavior of encoder_4to2 is
begin
  process(input)
  begin
    case input is
      when "0001" => output <= "00";
      when "0010" => output <= "01";
      when "0100" => output <= "10";
      when "1000" => output <= "11";
      when others => output <= "00"; -- default
    end case;
  end process;
end behavior;

This decoder activates one of eight outputs based on a 3-bit input.

VHDL

architecture behavior of decoder_3to8 is
begin
  process(input)
  begin
    output <= (others => '0');
    case input is
      when "000" => output(0) <= '1';
      when "001" => output(1) <= '1';
      when "010" => output(2) <= '1';
      when "011" => output(3) <= '1';
      when "100" => output(4) <= '1';
      when "101" => output(5) <= '1';
      when "110" => output(6) <= '1';
      when "111" => output(7) <= '1';
      when others => output <= (others => '0');
    end case;
  end process;
end behavior;

Sample Program

This program defines a 2-to-4 decoder and a testbench that cycles through all inputs. It prints the input number and the output vector showing which output line is active.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity decoder_2to4 is
  port(
    input : in std_logic_vector(1 downto 0);
    output : out std_logic_vector(3 downto 0)
  );
end decoder_2to4;

architecture behavior of decoder_2to4 is
begin
  process(input)
  begin
    output <= (others => '0');
    case input is
      when "00" => output(0) <= '1';
      when "01" => output(1) <= '1';
      when "10" => output(2) <= '1';
      when "11" => output(3) <= '1';
      when others => output <= (others => '0');
    end case;
  end process;
end behavior;

-- Testbench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_decoder is
end tb_decoder;

architecture test of tb_decoder is
  signal input : std_logic_vector(1 downto 0) := "00";
  signal output : std_logic_vector(3 downto 0);
begin
  uut: entity work.decoder_2to4
    port map(
      input => input,
      output => output
    );

  process
  begin
    for i in 0 to 3 loop
      input <= std_logic_vector(to_unsigned(i, 2));
      wait for 10 ns;
      report "Input: " & integer'image(i) & " Output: " & std_logic_vector(output).to_string;
    end loop;
    wait;
  end process;
end test;

Important Notes

Decoders usually have one active output line for each input code.

Encoders assume only one input line is active at a time to avoid confusion.

Use testbenches to verify your design by simulating different inputs.

Summary

A decoder turns a small input code into one active output line.

An encoder converts one active input line into a smaller output code.

Both are useful for selecting devices or compressing signals in digital circuits.