Aggregate assignment in VHDL

Introduction

Aggregate assignment lets you set many parts of a data object at once. It makes your code shorter and easier to read.

When you want to assign values to all elements of an array or record quickly.

When initializing a signal or variable with multiple fields at once.

When you want to update several parts of a record in one statement.

When you want to clearly show the values of each part of a complex data type.

Syntax

VHDL

variable_or_signal <= (element1 => value1, element2 => value2, ...);

You use parentheses and specify each element with => and its value.

This works for arrays and records in VHDL.

Examples

Assigns each bit of the vector individually using aggregate assignment.

VHDL

signal my_vector : std_logic_vector(3 downto 0);

my_vector <= (0 => '1', 1 => '0', 2 => '1', 3 => '0');

Assigns values to each field of a record at once.

VHDL

type my_record is record
  a : integer;
  b : std_logic;
end record;

signal rec : my_record;

rec <= (a => 10, b => '1');

Sample Program

This program assigns values to a 4-bit vector using aggregate assignment. Then it prints the vector value.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity aggregate_example is
end entity;

architecture behavior of aggregate_example is
  signal my_vector : std_logic_vector(3 downto 0);
begin
  process
  begin
    my_vector <= (0 => '1', 1 => '0', 2 => '1', 3 => '0');
    wait for 10 ns;
    report "my_vector = " & my_vector;
    wait;
  end process;
end architecture;

Important Notes

Aggregate assignment is very useful for clarity and reducing code repetition.

Make sure the elements you assign match the data type's structure exactly.

Summary

Aggregate assignment sets multiple parts of arrays or records at once.

It uses parentheses with element => value pairs.

This makes your VHDL code cleaner and easier to understand.