Entity-Architecture model in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare an entity named 'my_entity'.

VHDL

entity my_entity is
  port(
    clk : in std_logic;
    rst : in std_logic
  );
end [1];

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Aarchitecture

Bentity

Ccomponent

Dpackage

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'architecture' instead of 'entity' to declare the entity.

Forgetting to end the entity declaration properly.

The keyword 'entity' is used to declare the entity block in VHDL.

2fill in blank

medium

Complete the code to start an architecture named 'behavior' for entity 'my_entity'.

VHDL

architecture [1] of my_entity is
begin
  -- architecture body
end behavior;

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Abehavior

Brtl

Cstructural

Ddataflow

Attempts:

3 left

💡 Hint

Common Mistakes

Mismatching architecture name in the begin and end statements.

Using an architecture name that does not match the design style.

The architecture name 'behavior' matches the end statement and defines the architecture body.

3fill in blank

hard

Fix the error in the port declaration to correctly define an input signal 'data_in' of type std_logic_vector(7 downto 0).

VHDL

entity data_entity is
  port(
    data_in : [1] std_logic_vector(7 downto 0)
  );
end data_entity;

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Ain

Binout

Cout

Dbuffer

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'out' or 'buffer' for input signals.

Omitting the mode keyword before the type.

The signal 'data_in' is an input, so it must be declared with mode 'in'.

4fill in blank

hard

Fill both blanks to complete the architecture body that assigns 'output_signal' the value of 'input_signal'.

VHDL

architecture rtl of simple_entity is
begin
  process(clk)
  begin
    if rising_edge(clk) then
      [1] <= [2];
    end if;
  end process;
end rtl;

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Aoutput_signal

Binput_signal

Cclk

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Swapping the signals on the assignment operator.

Using clock or reset signals instead of data signals.

The output signal is assigned the value of the input signal inside the clocked process.

5fill in blank

hard

Fill all three blanks to complete the entity and architecture that defines a 1-bit AND gate.

VHDL

entity and_gate is
  port(
    a : [1] std_logic;
    b : [2] std_logic;
    y : [3] std_logic
  );
end and_gate;

architecture behavior of and_gate is
begin
  y <= a and b;
end behavior;

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Ain

Bout

Cbuffer

Dinout

Attempts:

3 left

💡 Hint

Common Mistakes

Declaring inputs as 'out' or 'buffer'.

Declaring output as 'in'.

Inputs 'a' and 'b' are declared as 'in', and output 'y' is declared as 'out'.