Logical operators (and, or, xor, not, nand, nor) in VHDL

Introduction

Logical operators help you combine or change true/false signals in digital circuits. They let you decide how signals work together.

To check if two signals are both true before turning on a light.

To turn on a device if at least one of several buttons is pressed.

To flip a signal from true to false or false to true.

To create complex conditions by combining simple true/false signals.

To build basic digital circuits like adders or multiplexers.

Syntax

VHDL

signal_name <= input1 and input2;
signal_name <= input1 or input2;
signal_name <= input1 xor input2;
signal_name <= not input1;
signal_name <= input1 nand input2;
signal_name <= input1 nor input2;

Logical operators work on signals that are 'std_logic' or 'boolean' types.

Use '<=' to assign the result of the operation to a signal.

Examples

This sets output_signal to true only if both a and b are true.

VHDL

output_signal <= a and b;

This sets output_signal to true if either a or b is true.

VHDL

output_signal <= a or b;

This flips the value of a. If a is true, output_signal becomes false, and vice versa.

VHDL

output_signal <= not a;

This sets output_signal to true if a and b are different.

VHDL

output_signal <= a xor b;

Sample Program

This VHDL code defines a simple circuit that takes two inputs a and b. It outputs the result of all main logical operations: and, or, xor, not (on a), nand, and nor.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity logic_ops_example is
    port(
        a : in std_logic;
        b : in std_logic;
        and_out : out std_logic;
        or_out : out std_logic;
        xor_out : out std_logic;
        not_out : out std_logic;
        nand_out : out std_logic;
        nor_out : out std_logic
    );
end logic_ops_example;

architecture behavior of logic_ops_example is
begin
    and_out <= a and b;
    or_out <= a or b;
    xor_out <= a xor b;
    not_out <= not a;
    nand_out <= a nand b;
    nor_out <= a nor b;
end behavior;

Important Notes

Logical operators in VHDL work bit by bit on std_logic signals.

not is a unary operator; it works on one input only.

nand and nor are just the opposite of and and or.

Summary

Logical operators combine or invert signals to create new signals.

Use and, or, xor, not, nand, and nor to build digital logic.

They are essential for controlling how signals interact in circuits.