Component instantiation in testbench in VHDL

Introduction

Component instantiation lets you use a design part inside a testbench to check if it works right.

When you want to test a small part of your design separately.

When you need to simulate how your design behaves with different inputs.

When you want to verify the outputs of a component before using it in a bigger system.

Syntax

VHDL

uut: entity work.ComponentName
  port map (
    signal1 => testbench_signal1,
    signal2 => testbench_signal2
  );

uut is a label you give to this instance, like a nickname.

entity work.ComponentName tells VHDL which design part to use.

Examples

This example connects signals in the testbench to the AndGate component ports.

VHDL

uut: entity work.AndGate
  port map (
    A => tb_A,
    B => tb_B,
    Y => tb_Y
  );

Here, the Adder component is used with testbench signals for inputs and output.

VHDL

myAdder: entity work.Adder
  port map (
    input1 => tb_input1,
    input2 => tb_input2,
    sum => tb_sum
  );

Sample Program

This testbench creates signals and connects them to an AndGate component. It changes inputs and shows the output using reports.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb_AndGate is
end tb_AndGate;

architecture behavior of tb_AndGate is
  signal tb_A, tb_B, tb_Y : std_logic := '0';

  -- Component instantiation
  uut: entity work.AndGate
    port map (
      A => tb_A,
      B => tb_B,
      Y => tb_Y
    );
begin
  process
  begin
    tb_A <= '0'; tb_B <= '0'; wait for 10 ns;
    report "A=0 B=0 Y=" & std_logic'image(tb_Y);

    tb_A <= '0'; tb_B <= '1'; wait for 10 ns;
    report "A=0 B=1 Y=" & std_logic'image(tb_Y);

    tb_A <= '1'; tb_B <= '0'; wait for 10 ns;
    report "A=1 B=0 Y=" & std_logic'image(tb_Y);

    tb_A <= '1'; tb_B <= '1'; wait for 10 ns;
    report "A=1 B=1 Y=" & std_logic'image(tb_Y);

    wait;
  end process;
end behavior;

Important Notes

Make sure the component (like AndGate) is compiled before the testbench.

Use clear signal names to avoid confusion between testbench and component signals.

Summary

Component instantiation lets you test parts of your design inside a testbench.

You connect testbench signals to component ports using port map.

This helps check if your design works as expected before building bigger systems.