Concurrent signal assignment in VHDL

Introduction

Concurrent signal assignment lets you set values to signals that update automatically and at the same time as other parts of your design.

When you want to update a signal based on other signals continuously.

When designing hardware circuits that need to react instantly to input changes.

When you want to describe simple logic like gates or combinational circuits.

When you want multiple signals to update independently but at the same time.

When you want your design to reflect real hardware behavior where many things happen together.

Syntax

VHDL

signal_name <= expression;

This assignment happens concurrently, meaning it runs all the time, not step-by-step.

The expression can use other signals or constants to calculate the new value.

Examples

This sets output_signal to the AND of two input signals continuously.

VHDL

output_signal <= input_signal1 AND input_signal2;

This assigns the sum of a and b to sum all the time.

VHDL

sum <= a + b;

This uses a conditional expression to assign flag based on condition.

VHDL

flag <= '1' when condition = '1' else '0';

Sample Program

This program defines a simple AND gate. The output c is assigned the AND of inputs a and b using concurrent signal assignment.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_and is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           c : out STD_LOGIC);
end simple_and;

architecture Behavioral of simple_and is
begin
    c <= a AND b;  -- concurrent signal assignment
end Behavioral;

Important Notes

Concurrent assignments happen all the time and in parallel, unlike sequential code inside processes.

Use concurrent assignments for simple combinational logic outside processes.

Remember that signals update after a small delay, not instantly.

Summary

Concurrent signal assignment sets signals continuously and in parallel.

It is used to describe combinational logic in hardware.

The syntax is simple: signal_name <= expression;