Entity-Architecture model in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is an Entity in VHDL?

An Entity defines the interface of a VHDL component. It declares the inputs and outputs (ports) that connect the component to the outside world.

beginner

What is an Architecture in VHDL?

An Architecture describes the internal behavior or structure of the Entity. It contains the code that defines how the component works.

beginner

How do Entity and Architecture relate in VHDL?

The Entity declares the component's interface, and the Architecture provides the implementation. Each Architecture is linked to one Entity by name.

beginner

What is the purpose of ports in an Entity?

Ports define the input and output signals of the component. They allow data to flow in and out, like plugs on a device.

intermediate

Can an Entity have multiple Architectures?

Yes, an Entity can have multiple Architectures. This lets you describe different implementations or behaviors for the same interface.

What does the Entity in VHDL define?

A The simulation environment

B The component's interface (inputs and outputs)

C The internal behavior of the component

D The clock frequency

The Entity defines the interface, including inputs and outputs (ports).

Where do you write the logic that describes how a VHDL component works?

A In the Entity

B In the Package

C In the Testbench

D In the Architecture

The Architecture contains the internal behavior or logic of the component.

Can one Entity have more than one Architecture in VHDL?

A Only if the Entity has no ports

B No, only one Architecture per Entity

C Yes, multiple Architectures are allowed

D Only in simulation

An Entity can have multiple Architectures to describe different implementations.

What keyword links an Architecture to its Entity?

A of

B architecture

C is

D entity

The keyword 'of' is used to link Architecture to the Entity, e.g., architecture Behavioral of MyEntity is ...

What do ports in an Entity represent?

A Input and output connections

B Internal signals

C Variables

D Constants

Ports are the inputs and outputs that connect the component to the outside.

Explain the roles of Entity and Architecture in VHDL and how they work together.

Think of Entity as the device's plugs and Architecture as the device's internal wiring.

Describe how you can use multiple Architectures for one Entity and why this might be useful.

Imagine different versions of a gadget with the same plugs but different insides.