Port modes tell us how signals can move in and out of a VHDL component. They help control data flow clearly.
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Port modes (in, out, inout, buffer) in VHDL
Introduction
When you want to send data into a component (use <code>in</code>).
When you want to send data out from a component (use <code>out</code>).
When you want a port to both receive and send data (use <code>inout</code>).
When you want to send data out and also use it inside the component (use <code>buffer</code>).
Syntax
VHDL
port_name : mode data_type;
mode can be in, out, inout, or buffer.
Each mode controls how the port can be read or written.
Examples
This port only receives data into the component.
VHDL
input_signal : in std_logic;This port only sends data out from the component.
VHDL
output_signal : out std_logic;
This port can both receive and send data.
VHDL
bidirectional_signal : inout std_logic;
This port sends data out and can be read inside the component.
VHDL
buffer_signal : buffer std_logic;
Sample Program
This example shows all four port modes in one component. It copies input a to output b and buffer d. The inout port c is assigned to itself to keep its value.
VHDL
library ieee; use ieee.std_logic_1164.all; entity port_modes_example is port( a : in std_logic; b : out std_logic; c : inout std_logic; d : buffer std_logic ); end port_modes_example; architecture behavior of port_modes_example is begin -- Pass input 'a' to output 'b' b <= a; -- For inout port 'c', just assign it to itself (no change) c <= c; -- For buffer port 'd', assign 'a' to 'd' d <= a; end behavior;
OutputSuccess
Important Notes
in ports cannot be assigned values inside the component.
out ports can only be assigned inside the component, but cannot be read.
buffer ports can be assigned and read inside the component, but are discouraged in newer VHDL versions.
inout ports are used for bidirectional signals like data buses.
Summary
in ports receive data only.
out ports send data only.
inout ports can do both receive and send.
buffer ports send data and can be read inside the component.