Entity-Architecture model in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple AND gate entity-architecture

What is the output of the following VHDL code when inputs A=1 and B=0?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AndGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end AndGate;

architecture Behavioral of AndGate is
begin
    Y <= A and B;
end Behavioral;

A Y = 'Z' (high impedance)

B Y = '1'

C Y = '0'

D Y = 'X' (unknown)

💡 Hint

AND gate outputs '1' only if both inputs are '1'.

Since input B is '0', the AND operation results in '0'.

🧠 Conceptual

intermediate

Purpose of the architecture block in VHDL

What is the main purpose of the architecture block in a VHDL entity-architecture model?

A To define the internal behavior or structure of the entity

B To specify the target hardware device

C To declare the input and output ports of the design

D To initialize simulation parameters

💡 Hint

Think about where the logic or circuit details are described.

The architecture block contains the actual logic or structure that implements the entity's function.

🔧 Debug

advanced

Identify the error in this entity-architecture code

What error will this VHDL code produce when compiled?

VHDL

entity OrGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end OrGate;

architecture Behavioral of OrGate is
begin
    Y <= A or B;
end Behavioral;

A No error, code compiles successfully

B SyntaxError: Missing semicolon after entity declaration

C TypeError: Cannot use 'or' operator on STD_LOGIC

D SyntaxError: Missing semicolon after end OrGate

💡 Hint

Check the entity declaration ending line carefully.

The entity declaration must end with a semicolon after 'end OrGate'.

📝 Syntax

advanced

Correct architecture declaration syntax

Which option shows the correct syntax to declare an architecture named 'DataPath' for an entity 'Processor'?

A architecture DataPath of Processor is begin end DataPath;

B architecture DataPath is of Processor begin end;

C architecture DataPath of Processor begin end DataPath;

D architecture DataPath of Processor is begin end;

💡 Hint

Remember the order: architecture name, of entity name, is, begin ... end;

The correct syntax is: architecture of is begin ... end ;

🚀 Application

expert

Number of signals in architecture after elaboration

Given this VHDL entity-architecture, how many signals are present inside the architecture after elaboration?

VHDL

entity Counter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count_out : out INTEGER range 0 to 15);
end Counter;

architecture Behavioral of Counter is
    signal count : INTEGER range 0 to 15 := 0;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            count <= 0;
        elsif rising_edge(clk) then
            count <= count + 1;
        end if;
    end process;
    count_out <= count;
end Behavioral;

A 0

B 1

C 3

D 2

💡 Hint

Count only signals declared inside the architecture block.

Only one signal named 'count' is declared inside the architecture.