Entity-Architecture model in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple AND gate entity-architecture

What is the output of the following VHDL code when inputs A=1 and B=0?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AndGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end AndGate;

architecture Behavioral of AndGate is
begin
    Y <= A and B;
end Behavioral;

A Y = 'Z' (high impedance)

B Y = '1'

C Y = '0'

D Y = 'X' (unknown)

💡 Hint

AND gate outputs '1' only if both inputs are '1'.

Since input B is '0', the AND operation results in '0'.

🧠 Conceptual

intermediate

Purpose of the architecture block in VHDL

What is the main purpose of the architecture block in a VHDL entity-architecture model?

A To define the internal behavior or structure of the entity

B To specify the target hardware device

C To declare the input and output ports of the design

D To initialize simulation parameters

💡 Hint

Think about where the logic or circuit details are described.

The architecture block contains the actual logic or structure that implements the entity's function.

🔧 Debug

advanced

Identify the error in this entity-architecture code

What error will this VHDL code produce when compiled?

VHDL

entity OrGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end OrGate;

architecture Behavioral of OrGate is
begin
    Y <= A or B;
end Behavioral;

A No error, code compiles successfully

B SyntaxError: Missing semicolon after entity declaration

C TypeError: Cannot use 'or' operator on STD_LOGIC

D SyntaxError: Missing semicolon after end OrGate

💡 Hint

Check the entity declaration ending line carefully.

The entity declaration must end with a semicolon after 'end OrGate'.

📝 Syntax

advanced

Correct architecture declaration syntax

Which option shows the correct syntax to declare an architecture named 'DataPath' for an entity 'Processor'?

A architecture DataPath of Processor is begin end DataPath;

B architecture DataPath is of Processor begin end;

C architecture DataPath of Processor begin end DataPath;

D architecture DataPath of Processor is begin end;

💡 Hint

Remember the order: architecture name, of entity name, is, begin ... end;

The correct syntax is: architecture of is begin ... end ;

🚀 Application

expert

Number of signals in architecture after elaboration

Given this VHDL entity-architecture, how many signals are present inside the architecture after elaboration?

VHDL

entity Counter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count_out : out INTEGER range 0 to 15);
end Counter;

architecture Behavioral of Counter is
    signal count : INTEGER range 0 to 15 := 0;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            count <= 0;
        elsif rising_edge(clk) then
            count <= count + 1;
        end if;
    end process;
    count_out <= count;
end Behavioral;

A 0

B 1

C 3

D 2

💡 Hint

Count only signals declared inside the architecture block.

Only one signal named 'count' is declared inside the architecture.

Practice

1. What is the main purpose of the entity in a VHDL design?

easy

A. To define the inputs and outputs of the circuit

B. To describe the internal behavior of the circuit

C. To specify the timing constraints

D. To declare variables used inside the circuit

Solution

1. Step 1: Understand the role of entity

   The entity defines the interface of the circuit, which means it lists all inputs and outputs.

2. Step 2: Differentiate from architecture

   The architecture describes how the circuit works inside, not the interface.

3. Final Answer:

   To define the inputs and outputs of the circuit -> Option A

4. Quick Check:

   Entity = Interface (inputs/outputs) [OK]

Hint: Entity = inputs and outputs, architecture = behavior [OK]

Common Mistakes:

• Confusing entity with architecture
• Thinking entity describes behavior
• Mixing interface with internal logic

2. Which of the following is the correct way to start an entity declaration in VHDL?

easy

A. entity design begin

B. architecture entity_name of design is

C. entity design is

D. architecture design is

Solution

1. Step 1: Recall entity declaration syntax

   The correct syntax to start an entity is: entity design_name is.

2. Step 2: Check options

   entity design is matches the correct syntax exactly. Other options confuse architecture and entity keywords or miss 'is'.

3. Final Answer:

   entity design is -> Option C

4. Quick Check:

   Entity declaration starts with 'entity name is' [OK]

Hint: Entity declaration always uses 'entity name is' [OK]

Common Mistakes:

• Using 'begin' instead of 'is' in entity
• Confusing entity and architecture keywords
• Starting entity with architecture keyword

3. Given the following VHDL code snippet, what is the output on out_signal when in_signal is '1'?

entity simple is
  port(in_signal : in std_logic; out_signal : out std_logic);
end simple;

architecture behavior of simple is
begin
  process(in_signal)
  begin
    if in_signal = '1' then
      out_signal <= '0';
    else
      out_signal <= '1';
    end if;
  end process;
end behavior;

medium

A. '1'

B. '0'

C. Undefined

D. Error

Solution

1. Step 1: Analyze the process behavior

   The process triggers on changes to in_signal. If in_signal is '1', out_signal is assigned '0'.

2. Step 2: Apply input value

   Given in_signal = '1', the condition is true, so out_signal becomes '0'.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Input '1' sets output '0' [OK]

Hint: Trace input through if condition to find output [OK]

Common Mistakes:

• Assuming output equals input directly
• Ignoring else branch
• Confusing signal assignment timing

4. Identify the error in the following VHDL code snippet:

entity test is
  port(a : in std_logic; b : out std_logic);
end test;

architecture arch of test is
begin
  process(a)
  begin
    if a = '1' then
      b <= '1'
    else
      b <= '0';
    end if;
  end process;
end arch;

medium

A. Missing semicolon after b <= '1'

B. Entity name does not match architecture name

C. Process sensitivity list is empty

D. Port directions are incorrect

Solution

1. Step 1: Check syntax inside process

   After b <= '1' there is no semicolon, which is required to end the statement.

2. Step 2: Verify other parts

   Entity and architecture names match, sensitivity list includes a, and port directions are correct.

3. Final Answer:

   Missing semicolon after b <= '1' -> Option A

4. Quick Check:

   Statements must end with semicolon [OK]

Hint: Check each statement ends with semicolon [OK]

Common Mistakes:

• Forgetting semicolon after signal assignment
• Confusing entity and architecture names
• Leaving sensitivity list empty

5. You want to create a VHDL module that has an entity with two inputs a and b and one output sum. The architecture should implement a simple 1-bit XOR gate. Which of the following architecture bodies correctly implements this behavior?

hard

A. architecture rtl of xor_gate is
begin
sum <= a and b;
end rtl;

B. architecture rtl of xor_gate is
begin
sum <= not (a and b);
end rtl;

C. architecture rtl of xor_gate is
begin
sum <= a or b;
end rtl;

D. architecture rtl of xor_gate is
begin
sum <= a xor b;
end rtl;

Solution

1. Step 1: Understand the required logic

   The output sum should be the XOR of inputs a and b.

2. Step 2: Match options to XOR behavior

   architecture rtl of xor_gate is begin sum <= a xor b; end rtl; uses a xor b, which is the correct XOR operation. Other options use AND, OR, or NAND-like logic.

3. Final Answer:

   architecture rtl of xor_gate is begin sum <= a xor b; end rtl; -> Option D

4. Quick Check:

   XOR gate uses 'xor' operator [OK]

Hint: XOR gate uses 'xor' keyword in architecture [OK]

Common Mistakes:

• Using 'and' or 'or' instead of 'xor'
• Confusing NOT with XOR
• Forgetting to assign output in architecture