Entity-Architecture model in VHDL - Time & Space Complexity
We want to understand how the time to run a VHDL design grows as the input size changes.
Specifically, we look at the Entity-Architecture model to see what parts repeat or take more time.
Analyze the time complexity of the following code snippet.
entity Counter is
port(
clk : in std_logic;
reset : in std_logic;
count_out : out integer
);
end Counter;
architecture Behavioral of Counter is
signal count : integer := 0;
begin
process(clk, reset)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;
count_out <= count;
end Behavioral;
This code defines a simple counter that increases its value on each clock cycle unless reset.
Identify the loops, recursion, array traversals that repeat.
- Primary operation: The process triggered on each clock edge increments the count.
- How many times: This happens once every clock cycle, repeating indefinitely.
Each clock cycle causes one increment operation, so the work grows directly with the number of cycles.
| Input Size (n) | Approx. Operations |
|---|---|
| 10 clock cycles | 10 increments |
| 100 clock cycles | 100 increments |
| 1000 clock cycles | 1000 increments |
Pattern observation: The number of operations grows linearly as the input (clock cycles) increases.
Time Complexity: O(n)
This means the time to run grows directly in proportion to the number of clock cycles.
[X] Wrong: "The counter increments instantly for all cycles at once."
[OK] Correct: Each increment happens one after another on each clock, so time grows with cycles, not all at once.
Understanding how hardware processes repeat over time helps you explain performance in digital designs clearly and confidently.
"What if we added a nested loop inside the process that counts up to a fixed number each cycle? How would the time complexity change?"