ALU design in VHDL

Introduction

An ALU (Arithmetic Logic Unit) is the part of a computer that does math and logic. It helps the computer make decisions and calculate numbers.

When you want to build a simple calculator inside a computer chip.

When you need to perform basic math like addition or subtraction in hardware.

When you want to compare two numbers to see which is bigger.

When designing a small CPU or processor for learning or projects.

When you want to combine math and logic operations in one unit.

Syntax

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is
    Port (
        A : in  STD_LOGIC_VECTOR(3 downto 0);
        B : in  STD_LOGIC_VECTOR(3 downto 0);
        ALU_Sel : in  STD_LOGIC_VECTOR(2 downto 0);
        Result : out  STD_LOGIC_VECTOR(3 downto 0);
        CarryOut : out STD_LOGIC
    );
end ALU;

architecture Behavioral of ALU is
begin
    process(A, B, ALU_Sel)
    variable temp_result : unsigned(4 downto 0);
    begin
        case ALU_Sel is
            when "000" =>  -- Addition
                temp_result := resize(unsigned(A), 5) + resize(unsigned(B), 5);
                Result <= std_logic_vector(temp_result(3 downto 0));
                CarryOut <= temp_result(4);
            when "001" =>  -- Subtraction
                temp_result := resize(unsigned(A), 5) - resize(unsigned(B), 5);
                Result <= std_logic_vector(temp_result(3 downto 0));
                CarryOut <= temp_result(4);
            when "010" =>  -- AND
                Result <= A and B;
                CarryOut <= '0';
            when "011" =>  -- OR
                Result <= A or B;
                CarryOut <= '0';
            when "100" =>  -- XOR
                Result <= A xor B;
                CarryOut <= '0';
            when others =>
                Result <= (others => '0');
                CarryOut <= '0';
        end case;
    end process;
end Behavioral;

The ALU has inputs A and B which are 4-bit numbers.

ALU_Sel chooses the operation: 000 for add, 001 for subtract, etc.

Examples

Use this to add two numbers.

VHDL

ALU_Sel = "000" -- This means the ALU will add A and B.

Use this to find bits that are 1 in both A and B.

VHDL

ALU_Sel = "010" -- This means the ALU will do a bitwise AND on A and B.

Use this to find the difference between two numbers.

VHDL

ALU_Sel = "001" -- This means the ALU will subtract B from A.

Sample Program

This program defines a simple ALU that can add, subtract, and do bitwise AND, OR, XOR on 4-bit numbers. The testbench runs some examples and prints the results.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is
    Port (
        A : in  STD_LOGIC_VECTOR(3 downto 0);
        B : in  STD_LOGIC_VECTOR(3 downto 0);
        ALU_Sel : in  STD_LOGIC_VECTOR(2 downto 0);
        Result : out  STD_LOGIC_VECTOR(3 downto 0);
        CarryOut : out STD_LOGIC
    );
end ALU;

architecture Behavioral of ALU is
begin
    process(A, B, ALU_Sel)
    variable temp_result : unsigned(4 downto 0);
    begin
        case ALU_Sel is
            when "000" =>  -- Addition
                temp_result := resize(unsigned(A), 5) + resize(unsigned(B), 5);
                Result <= std_logic_vector(temp_result(3 downto 0));
                CarryOut <= temp_result(4);
            when "001" =>  -- Subtraction
                temp_result := resize(unsigned(A), 5) - resize(unsigned(B), 5);
                Result <= std_logic_vector(temp_result(3 downto 0));
                CarryOut <= temp_result(4);
            when "010" =>  -- AND
                Result <= A and B;
                CarryOut <= '0';
            when "011" =>  -- OR
                Result <= A or B;
                CarryOut <= '0';
            when "100" =>  -- XOR
                Result <= A xor B;
                CarryOut <= '0';
            when others =>
                Result <= (others => '0');
                CarryOut <= '0';
        end case;
    end process;
end Behavioral;

-- Testbench to see ALU in action
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU_tb is
end ALU_tb;

architecture Behavioral of ALU_tb is
    signal A, B : STD_LOGIC_VECTOR(3 downto 0);
    signal ALU_Sel : STD_LOGIC_VECTOR(2 downto 0);
    signal Result : STD_LOGIC_VECTOR(3 downto 0);
    signal CarryOut : STD_LOGIC;
begin
    uut: entity work.ALU
        port map(
            A => A,
            B => B,
            ALU_Sel => ALU_Sel,
            Result => Result,
            CarryOut => CarryOut
        );

    process
    begin
        -- Test addition 3 + 5
        A <= "0011"; -- 3
        B <= "0101"; -- 5
        ALU_Sel <= "000"; -- add
        wait for 10 ns;
        report "Add 3 + 5 = " & integer'image(to_integer(unsigned(Result))) & ", CarryOut = " & std_logic'image(CarryOut);

        -- Test subtraction 7 - 2
        A <= "0111"; -- 7
        B <= "0010"; -- 2
        ALU_Sel <= "001"; -- subtract
        wait for 10 ns;
        report "Subtract 7 - 2 = " & integer'image(to_integer(unsigned(Result))) & ", CarryOut = " & std_logic'image(CarryOut);

        -- Test AND 6 & 3
        A <= "0110"; -- 6
        B <= "0011"; -- 3
        ALU_Sel <= "010"; -- AND
        wait for 10 ns;
        report "AND 6 & 3 = " & integer'image(to_integer(unsigned(Result))) & ", CarryOut = " & std_logic'image(CarryOut);

        -- Test OR 4 | 1
        A <= "0100"; -- 4
        B <= "0001"; -- 1
        ALU_Sel <= "011"; -- OR
        wait for 10 ns;
        report "OR 4 | 1 = " & integer'image(to_integer(unsigned(Result))) & ", CarryOut = " & std_logic'image(CarryOut);

        wait;
    end process;
end Behavioral;

Important Notes

CarryOut shows if there was a carry or borrow in addition or subtraction.

Use unsigned() to convert bits to numbers for math.

ALU_Sel controls which operation the ALU does.

Summary

An ALU does math and logic on numbers inside a chip.

You select the operation with a control signal (ALU_Sel).

VHDL lets you describe the ALU behavior clearly and test it.