ALU design in VHDL

Introduction

An ALU (Arithmetic Logic Unit) is the part of a computer that does math and logic. It helps the computer make decisions and calculate numbers.

When you want to build a simple calculator inside a computer chip.

When you need to perform basic math like addition or subtraction in hardware.

When you want to compare two numbers to see which is bigger.

When designing a small CPU or processor for learning or projects.

When you want to combine math and logic operations in one unit.

Syntax

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is
    Port (
        A : in  STD_LOGIC_VECTOR(3 downto 0);
        B : in  STD_LOGIC_VECTOR(3 downto 0);
        ALU_Sel : in  STD_LOGIC_VECTOR(2 downto 0);
        Result : out  STD_LOGIC_VECTOR(3 downto 0);
        CarryOut : out STD_LOGIC
    );
end ALU;

architecture Behavioral of ALU is
begin
    process(A, B, ALU_Sel)
    variable temp_result : unsigned(4 downto 0);
    begin
        case ALU_Sel is
            when "000" =>  -- Addition
                temp_result := resize(unsigned(A), 5) + resize(unsigned(B), 5);
                Result <= std_logic_vector(temp_result(3 downto 0));
                CarryOut <= temp_result(4);
            when "001" =>  -- Subtraction
                temp_result := resize(unsigned(A), 5) - resize(unsigned(B), 5);
                Result <= std_logic_vector(temp_result(3 downto 0));
                CarryOut <= temp_result(4);
            when "010" =>  -- AND
                Result <= A and B;
                CarryOut <= '0';
            when "011" =>  -- OR
                Result <= A or B;
                CarryOut <= '0';
            when "100" =>  -- XOR
                Result <= A xor B;
                CarryOut <= '0';
            when others =>
                Result <= (others => '0');
                CarryOut <= '0';
        end case;
    end process;
end Behavioral;

The ALU has inputs A and B which are 4-bit numbers.

ALU_Sel chooses the operation: 000 for add, 001 for subtract, etc.

Examples

Use this to add two numbers.

VHDL

ALU_Sel = "000" -- This means the ALU will add A and B.

Use this to find bits that are 1 in both A and B.

VHDL

ALU_Sel = "010" -- This means the ALU will do a bitwise AND on A and B.

Use this to find the difference between two numbers.

VHDL

ALU_Sel = "001" -- This means the ALU will subtract B from A.

Sample Program

This program defines a simple ALU that can add, subtract, and do bitwise AND, OR, XOR on 4-bit numbers. The testbench runs some examples and prints the results.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is
    Port (
        A : in  STD_LOGIC_VECTOR(3 downto 0);
        B : in  STD_LOGIC_VECTOR(3 downto 0);
        ALU_Sel : in  STD_LOGIC_VECTOR(2 downto 0);
        Result : out  STD_LOGIC_VECTOR(3 downto 0);
        CarryOut : out STD_LOGIC
    );
end ALU;

architecture Behavioral of ALU is
begin
    process(A, B, ALU_Sel)
    variable temp_result : unsigned(4 downto 0);
    begin
        case ALU_Sel is
            when "000" =>  -- Addition
                temp_result := resize(unsigned(A), 5) + resize(unsigned(B), 5);
                Result <= std_logic_vector(temp_result(3 downto 0));
                CarryOut <= temp_result(4);
            when "001" =>  -- Subtraction
                temp_result := resize(unsigned(A), 5) - resize(unsigned(B), 5);
                Result <= std_logic_vector(temp_result(3 downto 0));
                CarryOut <= temp_result(4);
            when "010" =>  -- AND
                Result <= A and B;
                CarryOut <= '0';
            when "011" =>  -- OR
                Result <= A or B;
                CarryOut <= '0';
            when "100" =>  -- XOR
                Result <= A xor B;
                CarryOut <= '0';
            when others =>
                Result <= (others => '0');
                CarryOut <= '0';
        end case;
    end process;
end Behavioral;

-- Testbench to see ALU in action
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU_tb is
end ALU_tb;

architecture Behavioral of ALU_tb is
    signal A, B : STD_LOGIC_VECTOR(3 downto 0);
    signal ALU_Sel : STD_LOGIC_VECTOR(2 downto 0);
    signal Result : STD_LOGIC_VECTOR(3 downto 0);
    signal CarryOut : STD_LOGIC;
begin
    uut: entity work.ALU
        port map(
            A => A,
            B => B,
            ALU_Sel => ALU_Sel,
            Result => Result,
            CarryOut => CarryOut
        );

    process
    begin
        -- Test addition 3 + 5
        A <= "0011"; -- 3
        B <= "0101"; -- 5
        ALU_Sel <= "000"; -- add
        wait for 10 ns;
        report "Add 3 + 5 = " & integer'image(to_integer(unsigned(Result))) & ", CarryOut = " & std_logic'image(CarryOut);

        -- Test subtraction 7 - 2
        A <= "0111"; -- 7
        B <= "0010"; -- 2
        ALU_Sel <= "001"; -- subtract
        wait for 10 ns;
        report "Subtract 7 - 2 = " & integer'image(to_integer(unsigned(Result))) & ", CarryOut = " & std_logic'image(CarryOut);

        -- Test AND 6 & 3
        A <= "0110"; -- 6
        B <= "0011"; -- 3
        ALU_Sel <= "010"; -- AND
        wait for 10 ns;
        report "AND 6 & 3 = " & integer'image(to_integer(unsigned(Result))) & ", CarryOut = " & std_logic'image(CarryOut);

        -- Test OR 4 | 1
        A <= "0100"; -- 4
        B <= "0001"; -- 1
        ALU_Sel <= "011"; -- OR
        wait for 10 ns;
        report "OR 4 | 1 = " & integer'image(to_integer(unsigned(Result))) & ", CarryOut = " & std_logic'image(CarryOut);

        wait;
    end process;
end Behavioral;

Important Notes

CarryOut shows if there was a carry or borrow in addition or subtraction.

Use unsigned() to convert bits to numbers for math.

ALU_Sel controls which operation the ALU does.

Summary

An ALU does math and logic on numbers inside a chip.

You select the operation with a control signal (ALU_Sel).

VHDL lets you describe the ALU behavior clearly and test it.

Practice

1. What is the main purpose of an ALU (Arithmetic Logic Unit) in a VHDL design?

easy

A. To perform arithmetic and logic operations on input data

B. To store data permanently

C. To control the flow of data between memory and CPU

D. To generate clock signals for synchronization

Solution

1. Step 1: Understand ALU function

   An ALU is designed to perform arithmetic (like addition) and logic (like AND, OR) operations on data inputs.

2. Step 2: Compare options with ALU role

   Only To perform arithmetic and logic operations on input data describes performing arithmetic and logic operations, which matches the ALU's purpose.

3. Final Answer:

   To perform arithmetic and logic operations on input data -> Option A

4. Quick Check:

   ALU = Arithmetic and Logic operations [OK]

Hint: ALU = math + logic on numbers inside chip [OK]

Common Mistakes:

• Confusing ALU with memory or control units
• Thinking ALU stores data permanently
• Assuming ALU generates clock signals

2. Which VHDL statement correctly selects an ALU operation based on a 2-bit control signal ALU_Sel?

easy

A. if ALU_Sel = 0 then result <= A + B; else result <= A - B; end if;

B. case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case;

C. switch(ALU_Sel) { case 0: result = A + B; break; case 1: result = A - B; }

D. select ALU_Sel when 0 => result <= A + B; when 1 => result <= A - B;

Solution

1. Step 1: Identify correct VHDL syntax for selection

   VHDL uses case ... is ... when ... => ... end case; for multi-way selection.

2. Step 2: Check options for correct syntax

   case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case; uses correct VHDL case syntax with bit string conditions. if ALU_Sel = 0 then result <= A + B; else result <= A - B; end if; uses if but compares to integer 0, which is invalid for std_logic_vector. switch(ALU_Sel) { case 0: result = A + B; break; case 1: result = A - B; } is not VHDL syntax (looks like C). select ALU_Sel when 0 => result <= A + B; when 1 => result <= A - B; uses invalid select syntax.

3. Final Answer:

   case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case; -> Option B

4. Quick Check:

   VHDL case syntax = case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case; [OK]

Hint: Use 'case ... is' for multi-bit control signals in VHDL [OK]

Common Mistakes:

• Using if with vector compared to integer
• Writing C-style switch in VHDL
• Incorrect select statement syntax

3. Given this VHDL snippet inside an ALU process:

case ALU_Sel is
  when "00" => result <= A + B;
  when "01" => result <= A and B;
  when others => result <= (others => '0');
end case;

If A = "1010", B = "1100", and ALU_Sel = "01", what is the value of result?

medium

A. "1000"

B. "1010"

C. "1110"

D. "0000"

Solution

1. Step 1: Identify operation for ALU_Sel = "01"

   The code says when ALU_Sel is "01", result <= A and B (bitwise AND).

2. Step 2: Calculate bitwise AND of A and B

   A = 1010, B = 1100
   Bitwise AND: 1&1=1, 0&1=0, 1&0=0, 0&0=0
   Result = 1000

3. Final Answer:

   "1000" -> Option A

4. Quick Check:

   Bitwise AND of 1010 & 1100 = 1000 [OK]

Hint: AND bits: 1&1=1 else 0 [OK]

Common Mistakes:

• Confusing AND with OR operation
• Mixing bit order in result
• Using decimal instead of binary

4. Identify the error in this VHDL ALU code snippet:

process(A, B, ALU_Sel)
begin
  case ALU_Sel is
    when "00" => result <= A + B;
    when "01" => result <= A - B;
    when others => result <= '0';
  end case;
end process;

medium

A. The case statement must use integers, not strings

B. The process sensitivity list is missing 'result'

C. The subtraction operator '-' is not allowed in VHDL

D. The 'when others' assignment uses a single bit '0' instead of a vector

Solution

1. Step 1: Check 'when others' assignment type

   The signal result is likely a vector (like std_logic_vector). Assigning a single bit '0' is a type mismatch.

2. Step 2: Confirm correct vector assignment

   To assign all bits zero, use (others => '0') instead of single '0'.

3. Final Answer:

   The 'when others' assignment uses a single bit '0' instead of a vector -> Option D

4. Quick Check:

   Vector needs (others => '0'), not '0' [OK]

Hint: Assign vectors with (others => '0'), not single quotes [OK]

Common Mistakes:

• Assigning single bit to vector signal
• Ignoring sensitivity list correctness
• Thinking '-' operator is invalid in VHDL

5. You want to extend an ALU to support a new operation: bitwise XOR when ALU_Sel = "10". Which VHDL code snippet correctly adds this operation inside the existing case statement?

case ALU_Sel is
  when "00" => result <= A + B;
  when "01" => result <= A - B;
  when others => result <= (others => '0');
end case;

hard

A. Add when "10" => result <= A or B; before when others

B. Replace when others with when "10" => result <= A xor B;

C. Add when "10" => result <= A xor B; before when others

D. Add when "10" => result <= A and B; after when others

Solution

1. Step 1: Understand case statement order

   Specific cases must be before when others because when others catches all unmatched cases.

2. Step 2: Add correct XOR operation for ALU_Sel = "10"

   Use when "10" => result <= A xor B; before when others to add XOR operation.

3. Final Answer:

   Add when "10" => result <= A xor B; before when others -> Option C

4. Quick Check:

   New case before others = Add when "10" => result <= A xor B; before when others [OK]

Hint: Put new cases before 'when others' in case statements [OK]

Common Mistakes:

• Replacing 'when others' instead of adding case
• Adding cases after 'when others' (ignored)
• Using wrong operation (OR or AND instead of XOR)