Adder and subtractor design in VHDL

Introduction

An adder and subtractor are basic circuits that add or subtract numbers. They help computers do math.

When you want to add two numbers in a digital circuit.

When you need to subtract one number from another in hardware.

When designing calculators or simple math units in electronics.

When building parts of a CPU that do arithmetic.

When learning how digital math works inside chips.

Syntax

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity AdderSubtractor is
  port(
    A, B : in std_logic_vector(3 downto 0);
    Sel : in std_logic; -- 0 for add, 1 for subtract
    Result : out std_logic_vector(3 downto 0);
    CarryOut : out std_logic
  );
end AdderSubtractor;

architecture Behavioral of AdderSubtractor is
begin
  process(A, B, Sel)
    variable B_mod : unsigned(3 downto 0);
    variable Sum : unsigned(4 downto 0);
  begin
    if Sel = '1' then
      B_mod := unsigned(not B) + 1; -- Two's complement for subtraction
    else
      B_mod := unsigned(B);
    end if;
    Sum := unsigned(A) + B_mod;
    Result <= std_logic_vector(Sum(3 downto 0));
    CarryOut <= Sum(4);
  end process;
end Behavioral;

This example uses std_logic_vector for inputs and outputs.

The Sel signal chooses addition (0) or subtraction (1).

Examples

When Sel is 0, the circuit adds the two inputs.

VHDL

Sel = '0' -- adds A and B
Result = A + B

When Sel is 1, the circuit subtracts B from A using two's complement.

VHDL

Sel = '1' -- subtracts B from A
Result = A - B

Sample Program

This program defines an adder-subtractor circuit and tests it with three cases: adding 5 and 3, subtracting 3 from 5, and subtracting 5 from 3 (which shows negative result in two's complement).

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity AdderSubtractor is
  port(
    A, B : in std_logic_vector(3 downto 0);
    Sel : in std_logic;
    Result : out std_logic_vector(3 downto 0);
    CarryOut : out std_logic
  );
end AdderSubtractor;

architecture Behavioral of AdderSubtractor is
begin
  process(A, B, Sel)
    variable B_mod : unsigned(3 downto 0);
    variable Sum : unsigned(4 downto 0);
  begin
    if Sel = '1' then
      B_mod := unsigned(not B) + 1; -- Two's complement for subtraction
    else
      B_mod := unsigned(B);
    end if;
    Sum := unsigned(A) + B_mod;
    Result <= std_logic_vector(Sum(3 downto 0));
    CarryOut <= Sum(4);
  end process;
end Behavioral;

-- Testbench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Testbench is
end Testbench;

architecture Behavioral of Testbench is
  signal A, B : std_logic_vector(3 downto 0);
  signal Sel : std_logic;
  signal Result : std_logic_vector(3 downto 0);
  signal CarryOut : std_logic;
begin
  UUT: entity work.AdderSubtractor
    port map(
      A => A,
      B => B,
      Sel => Sel,
      Result => Result,
      CarryOut => CarryOut
    );

  process
  begin
    -- Test addition 5 + 3
    A <= "0101"; -- 5
    B <= "0011"; -- 3
    Sel <= '0'; -- add
    wait for 10 ns;

    -- Test subtraction 5 - 3
    Sel <= '1'; -- subtract
    wait for 10 ns;

    -- Test subtraction 3 - 5 (negative result in 2's complement)
    A <= "0011"; -- 3
    B <= "0101"; -- 5
    Sel <= '1';
    wait for 10 ns;

    wait;
  end process;
end Behavioral;

Important Notes

Two's complement is used to represent negative numbers in subtraction.

CarryOut can indicate overflow or borrow depending on operation.

Make sure input sizes match to avoid errors.

Summary

An adder-subtractor circuit can add or subtract based on a control signal.

Subtraction is done by adding the two's complement of the number.

VHDL uses std_logic_vector and unsigned types to handle bits and math.

Practice

1. What is the main purpose of an adder-subtractor circuit in VHDL?

easy

A. To perform addition or subtraction based on a control signal

B. To multiply two numbers

C. To convert binary to decimal

D. To store data temporarily

Solution

1. Step 1: Understand the function of the circuit

   An adder-subtractor circuit can perform both addition and subtraction operations depending on a control input.

2. Step 2: Identify the correct purpose

   Since the circuit switches between adding and subtracting, its main purpose is to perform addition or subtraction based on a control signal.

3. Final Answer:

   To perform addition or subtraction based on a control signal -> Option A

4. Quick Check:

   Adder-subtractor = add or subtract [OK]

Hint: Adder-subtractor switches operation by control signal [OK]

Common Mistakes:

• Confusing adder-subtractor with multiplier
• Thinking it only adds
• Assuming it stores data

2. Which VHDL type is commonly used to represent binary numbers for arithmetic operations in an adder-subtractor?

easy

A. std_logic_vector

B. integer

C. bit

D. unsigned

Solution

1. Step 1: Identify types for arithmetic

   While std_logic_vector represents bits, it does not support arithmetic directly. The unsigned type allows arithmetic operations on bit vectors.

2. Step 2: Choose the correct type

   For addition and subtraction, unsigned is used to perform arithmetic on bit vectors.

3. Final Answer:

   unsigned -> Option D

4. Quick Check:

   Arithmetic on bits = unsigned type [OK]

Hint: Use unsigned for arithmetic on bit vectors [OK]

Common Mistakes:

• Using std_logic_vector directly for math
• Choosing integer which is not bit vector
• Using bit which is single bit only

3. Given this VHDL snippet for a 4-bit adder-subtractor:

signal A, B : unsigned(3 downto 0);
signal Result : unsigned(3 downto 0);
signal Subtract : std_logic;

Result <= A + (B xor (Subtract & Subtract & Subtract & Subtract)) + Subtract;

What operation does this code perform when Subtract = '1'?

medium

A. Adds A and B

B. Subtracts B from A

C. Performs bitwise AND of A and B

D. Performs bitwise OR of A and B

Solution

1. Step 1: Understand the XOR with Subtract signal

   When Subtract = '1', B is XORed with 1111 (all ones), which flips all bits of B (one's complement).

2. Step 2: Adding Subtract as carry-in

   Adding Subtract ('1') adds 1, completing two's complement of B, so Result = A + two's complement of B = A - B.

3. Final Answer:

   Subtracts B from A -> Option B

4. Quick Check:

   Subtract=1 means add two's complement = subtraction [OK]

Hint: XOR with all ones + 1 = two's complement subtraction [OK]

Common Mistakes:

• Ignoring the carry-in addition
• Thinking XOR flips bits but not adding 1
• Confusing addition with bitwise AND/OR

4. Identify the error in this VHDL code snippet for a subtractor:

Result <= A - B;
-- A and B are std_logic_vector(3 downto 0)

medium

A. Result signal is not declared

B. Missing semicolon after assignment

C. Cannot subtract std_logic_vector directly without conversion

D. Subtraction operator is invalid in VHDL

Solution

1. Step 1: Check types of A and B

   A and B are std_logic_vector, which do not support arithmetic operations directly.

2. Step 2: Identify correct usage

   To subtract, A and B must be converted to unsigned or signed types before subtraction.

3. Final Answer:

   Cannot subtract std_logic_vector directly without conversion -> Option C

4. Quick Check:

   std_logic_vector needs conversion for math [OK]

Hint: Convert std_logic_vector to unsigned before subtracting [OK]

Common Mistakes:

• Trying to subtract std_logic_vector directly
• Ignoring type conversions
• Assuming subtraction operator works on bits

5. You want to design a 4-bit adder-subtractor in VHDL that uses a control signal Sub to select addition (Sub='0') or subtraction (Sub='1'). Which of the following code snippets correctly implements this behavior?

hard

A. Result <= A + (B xor (Sub & Sub & Sub & Sub)) + Sub;

B. Result <= A + B when Sub = '0' else A - B;

C. Result <= A - (B xor (Sub & Sub & Sub & Sub)) - Sub;

D. Result <= A + B xor Sub;

Solution

1. Step 1: Understand two's complement subtraction

   Subtraction is done by adding two's complement of B, which is B XORed with all Sub bits plus Sub as carry-in.

2. Step 2: Analyze each option

   Result <= A + B when Sub = '0' else A - B; uses conditional assignment but does not handle two's complement properly. Result <= A + (B xor (Sub & Sub & Sub & Sub)) + Sub; correctly implements two's complement addition. Result <= A - (B xor (Sub & Sub & Sub & Sub)) - Sub; incorrectly subtracts after XOR. Result <= A + B xor Sub; applies XOR incorrectly.

3. Final Answer:

   Result <= A + (B xor (Sub & Sub & Sub & Sub)) + Sub; -> Option A

4. Quick Check:

   Two's complement subtraction = XOR + carry-in [OK]

Hint: Use XOR with control and add control as carry-in [OK]

Common Mistakes:

• Using conditional without two's complement
• Subtracting instead of adding two's complement
• Misusing XOR without carry-in