Adder and subtractor design in VHDL

Introduction

An adder and subtractor are basic circuits that add or subtract numbers. They help computers do math.

When you want to add two numbers in a digital circuit.

When you need to subtract one number from another in hardware.

When designing calculators or simple math units in electronics.

When building parts of a CPU that do arithmetic.

When learning how digital math works inside chips.

Syntax

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity AdderSubtractor is
  port(
    A, B : in std_logic_vector(3 downto 0);
    Sel : in std_logic; -- 0 for add, 1 for subtract
    Result : out std_logic_vector(3 downto 0);
    CarryOut : out std_logic
  );
end AdderSubtractor;

architecture Behavioral of AdderSubtractor is
begin
  process(A, B, Sel)
    variable B_mod : unsigned(3 downto 0);
    variable Sum : unsigned(4 downto 0);
  begin
    if Sel = '1' then
      B_mod := unsigned(not B) + 1; -- Two's complement for subtraction
    else
      B_mod := unsigned(B);
    end if;
    Sum := unsigned(A) + B_mod;
    Result <= std_logic_vector(Sum(3 downto 0));
    CarryOut <= Sum(4);
  end process;
end Behavioral;

This example uses std_logic_vector for inputs and outputs.

The Sel signal chooses addition (0) or subtraction (1).

Examples

When Sel is 0, the circuit adds the two inputs.

VHDL

Sel = '0' -- adds A and B
Result = A + B

When Sel is 1, the circuit subtracts B from A using two's complement.

VHDL

Sel = '1' -- subtracts B from A
Result = A - B

Sample Program

This program defines an adder-subtractor circuit and tests it with three cases: adding 5 and 3, subtracting 3 from 5, and subtracting 5 from 3 (which shows negative result in two's complement).

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity AdderSubtractor is
  port(
    A, B : in std_logic_vector(3 downto 0);
    Sel : in std_logic;
    Result : out std_logic_vector(3 downto 0);
    CarryOut : out std_logic
  );
end AdderSubtractor;

architecture Behavioral of AdderSubtractor is
begin
  process(A, B, Sel)
    variable B_mod : unsigned(3 downto 0);
    variable Sum : unsigned(4 downto 0);
  begin
    if Sel = '1' then
      B_mod := unsigned(not B) + 1; -- Two's complement for subtraction
    else
      B_mod := unsigned(B);
    end if;
    Sum := unsigned(A) + B_mod;
    Result <= std_logic_vector(Sum(3 downto 0));
    CarryOut <= Sum(4);
  end process;
end Behavioral;

-- Testbench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Testbench is
end Testbench;

architecture Behavioral of Testbench is
  signal A, B : std_logic_vector(3 downto 0);
  signal Sel : std_logic;
  signal Result : std_logic_vector(3 downto 0);
  signal CarryOut : std_logic;
begin
  UUT: entity work.AdderSubtractor
    port map(
      A => A,
      B => B,
      Sel => Sel,
      Result => Result,
      CarryOut => CarryOut
    );

  process
  begin
    -- Test addition 5 + 3
    A <= "0101"; -- 5
    B <= "0011"; -- 3
    Sel <= '0'; -- add
    wait for 10 ns;

    -- Test subtraction 5 - 3
    Sel <= '1'; -- subtract
    wait for 10 ns;

    -- Test subtraction 3 - 5 (negative result in 2's complement)
    A <= "0011"; -- 3
    B <= "0101"; -- 5
    Sel <= '1';
    wait for 10 ns;

    wait;
  end process;
end Behavioral;

Important Notes

Two's complement is used to represent negative numbers in subtraction.

CarryOut can indicate overflow or borrow depending on operation.

Make sure input sizes match to avoid errors.

Summary

An adder-subtractor circuit can add or subtract based on a control signal.

Subtraction is done by adding the two's complement of the number.

VHDL uses std_logic_vector and unsigned types to handle bits and math.