Entity-Architecture model in VHDL

Introduction

The Entity-Architecture model in VHDL helps you describe what a digital circuit looks like and how it works separately. This makes your design clear and easy to understand.

When you want to describe a digital circuit's inputs and outputs clearly.

When you want to separate the circuit's interface from its behavior.

When you need to reuse the same interface with different internal designs.

When you want to organize your VHDL code for easier reading and debugging.

Syntax

VHDL

entity EntityName is
    port(
        input1 : in std_logic;
        output1 : out std_logic
    );
end EntityName;

architecture ArchitectureName of EntityName is
begin
    -- behavior description here
end ArchitectureName;

The entity defines the circuit's interface (inputs and outputs).

The architecture describes how the circuit works inside.

Examples

This example shows a simple LED blinker entity with a clock input and LED output, and a behavioral architecture placeholder.

VHDL

entity LED_Blinker is
    port(
        clk : in std_logic;
        led : out std_logic
    );
end LED_Blinker;

architecture Behavioral of LED_Blinker is
begin
    -- blinking logic here
end Behavioral;

This example shows an AND gate entity and a dataflow architecture that connects inputs A and B to output Y using the AND operation.

VHDL

entity AND_Gate is
    port(
        A : in std_logic;
        B : in std_logic;
        Y : out std_logic
    );
end AND_Gate;

architecture Dataflow of AND_Gate is
begin
    Y <= A and B;
end Dataflow;

Sample Program

This program defines a simple inverter circuit. The entity declares one input A and one output Y. The architecture describes that Y is the opposite (NOT) of A.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Simple_Inverter is
    port(
        A : in std_logic;
        Y : out std_logic
    );
end Simple_Inverter;

architecture Behavioral of Simple_Inverter is
begin
    Y <= not A;
end Behavioral;

Important Notes

Always match the entity name with the architecture's entity reference.

You can have multiple architectures for one entity to describe different behaviors.

Use meaningful names for entities and architectures to keep your code clear.

Summary

The entity defines the circuit's inputs and outputs.

The architecture describes how the circuit behaves inside.

Separating interface and behavior helps organize and reuse your VHDL code.

Practice

1. What is the main purpose of the entity in a VHDL design?

easy

A. To define the inputs and outputs of the circuit

B. To describe the internal behavior of the circuit

C. To specify the timing constraints

D. To declare variables used inside the circuit

Solution

1. Step 1: Understand the role of entity

   The entity defines the interface of the circuit, which means it lists all inputs and outputs.

2. Step 2: Differentiate from architecture

   The architecture describes how the circuit works inside, not the interface.

3. Final Answer:

   To define the inputs and outputs of the circuit -> Option A

4. Quick Check:

   Entity = Interface (inputs/outputs) [OK]

Hint: Entity = inputs and outputs, architecture = behavior [OK]

Common Mistakes:

• Confusing entity with architecture
• Thinking entity describes behavior
• Mixing interface with internal logic

2. Which of the following is the correct way to start an entity declaration in VHDL?

easy

A. entity design begin

B. architecture entity_name of design is

C. entity design is

D. architecture design is

Solution

1. Step 1: Recall entity declaration syntax

   The correct syntax to start an entity is: entity design_name is.

2. Step 2: Check options

   entity design is matches the correct syntax exactly. Other options confuse architecture and entity keywords or miss 'is'.

3. Final Answer:

   entity design is -> Option C

4. Quick Check:

   Entity declaration starts with 'entity name is' [OK]

Hint: Entity declaration always uses 'entity name is' [OK]

Common Mistakes:

• Using 'begin' instead of 'is' in entity
• Confusing entity and architecture keywords
• Starting entity with architecture keyword

3. Given the following VHDL code snippet, what is the output on out_signal when in_signal is '1'?

entity simple is
  port(in_signal : in std_logic; out_signal : out std_logic);
end simple;

architecture behavior of simple is
begin
  process(in_signal)
  begin
    if in_signal = '1' then
      out_signal <= '0';
    else
      out_signal <= '1';
    end if;
  end process;
end behavior;

medium

A. '1'

B. '0'

C. Undefined

D. Error

Solution

1. Step 1: Analyze the process behavior

   The process triggers on changes to in_signal. If in_signal is '1', out_signal is assigned '0'.

2. Step 2: Apply input value

   Given in_signal = '1', the condition is true, so out_signal becomes '0'.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Input '1' sets output '0' [OK]

Hint: Trace input through if condition to find output [OK]

Common Mistakes:

• Assuming output equals input directly
• Ignoring else branch
• Confusing signal assignment timing

4. Identify the error in the following VHDL code snippet:

entity test is
  port(a : in std_logic; b : out std_logic);
end test;

architecture arch of test is
begin
  process(a)
  begin
    if a = '1' then
      b <= '1'
    else
      b <= '0';
    end if;
  end process;
end arch;

medium

A. Missing semicolon after b <= '1'

B. Entity name does not match architecture name

C. Process sensitivity list is empty

D. Port directions are incorrect

Solution

1. Step 1: Check syntax inside process

   After b <= '1' there is no semicolon, which is required to end the statement.

2. Step 2: Verify other parts

   Entity and architecture names match, sensitivity list includes a, and port directions are correct.

3. Final Answer:

   Missing semicolon after b <= '1' -> Option A

4. Quick Check:

   Statements must end with semicolon [OK]

Hint: Check each statement ends with semicolon [OK]

Common Mistakes:

• Forgetting semicolon after signal assignment
• Confusing entity and architecture names
• Leaving sensitivity list empty

5. You want to create a VHDL module that has an entity with two inputs a and b and one output sum. The architecture should implement a simple 1-bit XOR gate. Which of the following architecture bodies correctly implements this behavior?

hard

A. architecture rtl of xor_gate is
begin
sum <= a and b;
end rtl;

B. architecture rtl of xor_gate is
begin
sum <= not (a and b);
end rtl;

C. architecture rtl of xor_gate is
begin
sum <= a or b;
end rtl;

D. architecture rtl of xor_gate is
begin
sum <= a xor b;
end rtl;

Solution

1. Step 1: Understand the required logic

   The output sum should be the XOR of inputs a and b.

2. Step 2: Match options to XOR behavior

   architecture rtl of xor_gate is begin sum <= a xor b; end rtl; uses a xor b, which is the correct XOR operation. Other options use AND, OR, or NAND-like logic.

3. Final Answer:

   architecture rtl of xor_gate is begin sum <= a xor b; end rtl; -> Option D

4. Quick Check:

   XOR gate uses 'xor' operator [OK]

Hint: XOR gate uses 'xor' keyword in architecture [OK]

Common Mistakes:

• Using 'and' or 'or' instead of 'xor'
• Confusing NOT with XOR
• Forgetting to assign output in architecture