Entity-Architecture model in VHDL

Introduction

The Entity-Architecture model in VHDL helps you describe what a digital circuit looks like and how it works separately. This makes your design clear and easy to understand.

When you want to describe a digital circuit's inputs and outputs clearly.

When you want to separate the circuit's interface from its behavior.

When you need to reuse the same interface with different internal designs.

When you want to organize your VHDL code for easier reading and debugging.

Syntax

VHDL

entity EntityName is
    port(
        input1 : in std_logic;
        output1 : out std_logic
    );
end EntityName;

architecture ArchitectureName of EntityName is
begin
    -- behavior description here
end ArchitectureName;

The entity defines the circuit's interface (inputs and outputs).

The architecture describes how the circuit works inside.

Examples

This example shows a simple LED blinker entity with a clock input and LED output, and a behavioral architecture placeholder.

VHDL

entity LED_Blinker is
    port(
        clk : in std_logic;
        led : out std_logic
    );
end LED_Blinker;

architecture Behavioral of LED_Blinker is
begin
    -- blinking logic here
end Behavioral;

This example shows an AND gate entity and a dataflow architecture that connects inputs A and B to output Y using the AND operation.

VHDL

entity AND_Gate is
    port(
        A : in std_logic;
        B : in std_logic;
        Y : out std_logic
    );
end AND_Gate;

architecture Dataflow of AND_Gate is
begin
    Y <= A and B;
end Dataflow;

Sample Program

This program defines a simple inverter circuit. The entity declares one input A and one output Y. The architecture describes that Y is the opposite (NOT) of A.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Simple_Inverter is
    port(
        A : in std_logic;
        Y : out std_logic
    );
end Simple_Inverter;

architecture Behavioral of Simple_Inverter is
begin
    Y <= not A;
end Behavioral;

Important Notes

Always match the entity name with the architecture's entity reference.

You can have multiple architectures for one entity to describe different behaviors.

Use meaningful names for entities and architectures to keep your code clear.

Summary

The entity defines the circuit's inputs and outputs.

The architecture describes how the circuit behaves inside.

Separating interface and behavior helps organize and reuse your VHDL code.