Entity-Architecture model in VHDL - Mini Project: Build & Apply

Entity-Architecture Model in VHDL

📖 Scenario: You are designing a simple digital circuit that adds two 4-bit numbers. To organize your design, you will use the VHDL Entity-Architecture model. This helps separate the interface (inputs and outputs) from the internal behavior.

🎯 Goal: Create a VHDL design using the Entity-Architecture model that adds two 4-bit inputs and produces a 4-bit sum output.

📋 What You'll Learn

Create an entity named Adder4bit with two 4-bit input ports named A and B and one 4-bit output port named Sum.

Declare a signal named temp_sum of type std_logic_vector(4 downto 0) to hold the intermediate sum including carry.

In the architecture named Behavior, assign temp_sum to the sum of inputs A and B converted to unsigned integers.

Assign the lower 4 bits of temp_sum to the output port Sum.

Print the final VHDL code that includes the entity and architecture.

💡 Why This Matters

🌍 Real World

Digital circuits like adders are fundamental building blocks in computers and electronics. Using the Entity-Architecture model helps organize designs clearly.

💼 Career

Understanding VHDL and the Entity-Architecture model is essential for hardware engineers and FPGA developers who design and test digital systems.

1

Create the Entity

Write the VHDL entity named Adder4bit with input ports A and B as std_logic_vector(3 downto 0) and output port Sum as std_logic_vector(3 downto 0).

VHDL

-- Your code here

Hint

Remember, the entity defines the inputs and outputs of your circuit.

2

Add a Signal for Intermediate Sum

Add a signal named temp_sum of type std_logic_vector(4 downto 0) inside the architecture to hold the sum including carry.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Adder4bit is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sum : out std_logic_vector(3 downto 0)
    );
end Adder4bit;

architecture Behavior of Adder4bit is
    -- Your code here

Hint

Signals are declared inside the architecture but before the begin keyword.

3

Add the Core Logic to Sum Inputs

Inside the architecture Behavior, assign temp_sum to the sum of A and B converted to unsigned using unsigned(A) + unsigned(B). Use std_logic_vector to convert the result back.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Adder4bit is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sum : out std_logic_vector(3 downto 0)
    );
end Adder4bit;

architecture Behavior of Adder4bit is
    signal temp_sum : std_logic_vector(4 downto 0);
begin
    -- Your code here
end Behavior;

Hint

Use the unsigned type conversion from numeric_std to add the vectors.

4

Assign the Output and Print the Result

Assign the lower 4 bits of temp_sum to the output port Sum using Sum <= temp_sum(3 downto 0);. Then print the entire VHDL code.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Adder4bit is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sum : out std_logic_vector(3 downto 0)
    );
end Adder4bit;

architecture Behavior of Adder4bit is
    signal temp_sum : std_logic_vector(4 downto 0);
begin
    temp_sum <= std_logic_vector(unsigned(A) + unsigned(B));
    -- Your code here
end Behavior;

Hint

Assign the output port after computing the sum signal.

Practice

1. What is the main purpose of the entity in a VHDL design?

easy

A. To define the inputs and outputs of the circuit

B. To describe the internal behavior of the circuit

C. To specify the timing constraints

D. To declare variables used inside the circuit

Solution

1. Step 1: Understand the role of entity

   The entity defines the interface of the circuit, which means it lists all inputs and outputs.

2. Step 2: Differentiate from architecture

   The architecture describes how the circuit works inside, not the interface.

3. Final Answer:

   To define the inputs and outputs of the circuit -> Option A

4. Quick Check:

   Entity = Interface (inputs/outputs) [OK]

Hint: Entity = inputs and outputs, architecture = behavior [OK]

Common Mistakes:

• Confusing entity with architecture
• Thinking entity describes behavior
• Mixing interface with internal logic

2. Which of the following is the correct way to start an entity declaration in VHDL?

easy

A. entity design begin

B. architecture entity_name of design is

C. entity design is

D. architecture design is

Solution

1. Step 1: Recall entity declaration syntax

   The correct syntax to start an entity is: entity design_name is.

2. Step 2: Check options

   entity design is matches the correct syntax exactly. Other options confuse architecture and entity keywords or miss 'is'.

3. Final Answer:

   entity design is -> Option C

4. Quick Check:

   Entity declaration starts with 'entity name is' [OK]

Hint: Entity declaration always uses 'entity name is' [OK]

Common Mistakes:

• Using 'begin' instead of 'is' in entity
• Confusing entity and architecture keywords
• Starting entity with architecture keyword

3. Given the following VHDL code snippet, what is the output on out_signal when in_signal is '1'?

entity simple is
  port(in_signal : in std_logic; out_signal : out std_logic);
end simple;

architecture behavior of simple is
begin
  process(in_signal)
  begin
    if in_signal = '1' then
      out_signal <= '0';
    else
      out_signal <= '1';
    end if;
  end process;
end behavior;

medium

A. '1'

B. '0'

C. Undefined

D. Error

Solution

1. Step 1: Analyze the process behavior

   The process triggers on changes to in_signal. If in_signal is '1', out_signal is assigned '0'.

2. Step 2: Apply input value

   Given in_signal = '1', the condition is true, so out_signal becomes '0'.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Input '1' sets output '0' [OK]

Hint: Trace input through if condition to find output [OK]

Common Mistakes:

• Assuming output equals input directly
• Ignoring else branch
• Confusing signal assignment timing

4. Identify the error in the following VHDL code snippet:

entity test is
  port(a : in std_logic; b : out std_logic);
end test;

architecture arch of test is
begin
  process(a)
  begin
    if a = '1' then
      b <= '1'
    else
      b <= '0';
    end if;
  end process;
end arch;

medium

A. Missing semicolon after b <= '1'

B. Entity name does not match architecture name

C. Process sensitivity list is empty

D. Port directions are incorrect

Solution

1. Step 1: Check syntax inside process

   After b <= '1' there is no semicolon, which is required to end the statement.

2. Step 2: Verify other parts

   Entity and architecture names match, sensitivity list includes a, and port directions are correct.

3. Final Answer:

   Missing semicolon after b <= '1' -> Option A

4. Quick Check:

   Statements must end with semicolon [OK]

Hint: Check each statement ends with semicolon [OK]

Common Mistakes:

• Forgetting semicolon after signal assignment
• Confusing entity and architecture names
• Leaving sensitivity list empty

5. You want to create a VHDL module that has an entity with two inputs a and b and one output sum. The architecture should implement a simple 1-bit XOR gate. Which of the following architecture bodies correctly implements this behavior?

hard

A. architecture rtl of xor_gate is
begin
sum <= a and b;
end rtl;

B. architecture rtl of xor_gate is
begin
sum <= not (a and b);
end rtl;

C. architecture rtl of xor_gate is
begin
sum <= a or b;
end rtl;

D. architecture rtl of xor_gate is
begin
sum <= a xor b;
end rtl;

Solution

1. Step 1: Understand the required logic

   The output sum should be the XOR of inputs a and b.

2. Step 2: Match options to XOR behavior

   architecture rtl of xor_gate is begin sum <= a xor b; end rtl; uses a xor b, which is the correct XOR operation. Other options use AND, OR, or NAND-like logic.

3. Final Answer:

   architecture rtl of xor_gate is begin sum <= a xor b; end rtl; -> Option D

4. Quick Check:

   XOR gate uses 'xor' operator [OK]

Hint: XOR gate uses 'xor' keyword in architecture [OK]

Common Mistakes:

• Using 'and' or 'or' instead of 'xor'
• Confusing NOT with XOR
• Forgetting to assign output in architecture