Entity-Architecture model in VHDL - Mini Project: Build & Apply

Entity-Architecture Model in VHDL

📖 Scenario: You are designing a simple digital circuit that adds two 4-bit numbers. To organize your design, you will use the VHDL Entity-Architecture model. This helps separate the interface (inputs and outputs) from the internal behavior.

🎯 Goal: Create a VHDL design using the Entity-Architecture model that adds two 4-bit inputs and produces a 4-bit sum output.

📋 What You'll Learn

Create an entity named Adder4bit with two 4-bit input ports named A and B and one 4-bit output port named Sum.

Declare a signal named temp_sum of type std_logic_vector(4 downto 0) to hold the intermediate sum including carry.

In the architecture named Behavior, assign temp_sum to the sum of inputs A and B converted to unsigned integers.

Assign the lower 4 bits of temp_sum to the output port Sum.

Print the final VHDL code that includes the entity and architecture.

💡 Why This Matters

🌍 Real World

Digital circuits like adders are fundamental building blocks in computers and electronics. Using the Entity-Architecture model helps organize designs clearly.

💼 Career

Understanding VHDL and the Entity-Architecture model is essential for hardware engineers and FPGA developers who design and test digital systems.

1

Create the Entity

Write the VHDL entity named Adder4bit with input ports A and B as std_logic_vector(3 downto 0) and output port Sum as std_logic_vector(3 downto 0).

VHDL

-- Your code here

Need a hint?

Remember, the entity defines the inputs and outputs of your circuit.

2

Add a Signal for Intermediate Sum

Add a signal named temp_sum of type std_logic_vector(4 downto 0) inside the architecture to hold the sum including carry.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Adder4bit is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sum : out std_logic_vector(3 downto 0)
    );
end Adder4bit;

architecture Behavior of Adder4bit is
    -- Your code here

Need a hint?

Signals are declared inside the architecture but before the begin keyword.

3

Add the Core Logic to Sum Inputs

Inside the architecture Behavior, assign temp_sum to the sum of A and B converted to unsigned using unsigned(A) + unsigned(B). Use std_logic_vector to convert the result back.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Adder4bit is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sum : out std_logic_vector(3 downto 0)
    );
end Adder4bit;

architecture Behavior of Adder4bit is
    signal temp_sum : std_logic_vector(4 downto 0);
begin
    -- Your code here
end Behavior;

Need a hint?

Use the unsigned type conversion from numeric_std to add the vectors.

4

Assign the Output and Print the Result

Assign the lower 4 bits of temp_sum to the output port Sum using Sum <= temp_sum(3 downto 0);. Then print the entire VHDL code.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Adder4bit is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sum : out std_logic_vector(3 downto 0)
    );
end Adder4bit;

architecture Behavior of Adder4bit is
    signal temp_sum : std_logic_vector(4 downto 0);
begin
    temp_sum <= std_logic_vector(unsigned(A) + unsigned(B));
    -- Your code here
end Behavior;

Need a hint?

Assign the output port after computing the sum signal.