Library and use clause in VHDL

Introduction

The library and use clauses in VHDL help you include and access external code parts, like packages or components, so you can reuse them in your design.

When you want to use predefined components or packages in your VHDL design.

When you need to organize your code by separating reusable parts into libraries.

When you want to access standard VHDL packages like <code>ieee</code> for math or logic operations.

When you want to share code between multiple VHDL files or projects.

When you want to avoid rewriting common functions or types.

Syntax

VHDL

library library_name;
use library_name.package_name.all;

The library clause tells VHDL where to find the code.

The use clause tells VHDL which parts of that library you want to use.

Examples

This includes the standard IEEE library and its std_logic_1164 package, which defines common logic types.

VHDL

library ieee;
use ieee.std_logic_1164.all;

This uses a package called my_package from your current project library named work.

VHDL

library work;
use work.my_package.all;

This accesses all definitions inside the my_components package from the my_lib library.

VHDL

library my_lib;
use my_lib.my_components.all;

Sample Program

This program uses the IEEE library and its std_logic_1164 package to define the std_logic type. It creates a simple AND gate entity that outputs the AND of inputs a and b.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity simple_and is
    port(
        a : in std_logic;
        b : in std_logic;
        y : out std_logic
    );
end simple_and;

architecture behavior of simple_and is
begin
    y <= a and b;
end behavior;

Important Notes

The library clause must come before the use clause.

The work library is the default library for your current project files.

Using all imports everything from the package, but you can also import specific items if needed.

Summary

The library clause tells VHDL where to find code libraries.

The use clause lets you access specific packages or parts inside those libraries.

They help you reuse code and organize your VHDL designs better.