Priority encoder in VHDL

Introduction

A priority encoder helps find the highest priority input that is active. It turns many inputs into a smaller output code showing which input is the most important.

When you have multiple signals and want to know which one is active first.

In digital circuits to reduce many input lines to fewer output lines.

To decide which interrupt to handle first in a microcontroller.

When you want to encode the position of the first '1' in a set of bits.

Syntax

VHDL

entity PriorityEncoder is
    Port (
        inputs : in std_logic_vector(3 downto 0);
        output : out std_logic_vector(1 downto 0);
        valid : out std_logic
    );
end PriorityEncoder;

architecture Behavioral of PriorityEncoder is
begin
    process(inputs)
    begin
        if inputs(3) = '1' then
            output <= "11";
            valid <= '1';
        elsif inputs(2) = '1' then
            output <= "10";
            valid <= '1';
        elsif inputs(1) = '1' then
            output <= "01";
            valid <= '1';
        elsif inputs(0) = '1' then
            output <= "00";
            valid <= '1';
        else
            output <= "00";
            valid <= '0';
        end if;
    end process;
end Behavioral;

The inputs are checked from highest to lowest priority.

The output shows the position of the highest priority input that is '1'.

Examples

Checking inputs from highest bit 7 down to lower bits.

VHDL

if inputs(7) = '1' then
    output <= "111";
elsif inputs(6) = '1' then
    output <= "110";
-- and so on

Using case statement for fixed input patterns.

VHDL

process(inputs)
begin
    case inputs is
        when "1000" => output <= "11";
        when "0100" => output <= "10";
        when others => output <= "00";
    end case;
end process;

Sample Program

This program defines a priority encoder with 4 inputs. It outputs the position of the highest '1' bit and a valid signal. The testbench applies different inputs to see how the encoder responds.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity PriorityEncoder is
    Port (
        inputs : in std_logic_vector(3 downto 0);
        output : out std_logic_vector(1 downto 0);
        valid : out std_logic
    );
end PriorityEncoder;

architecture Behavioral of PriorityEncoder is
begin
    process(inputs)
    begin
        if inputs(3) = '1' then
            output <= "11";
            valid <= '1';
        elsif inputs(2) = '1' then
            output <= "10";
            valid <= '1';
        elsif inputs(1) = '1' then
            output <= "01";
            valid <= '1';
        elsif inputs(0) = '1' then
            output <= "00";
            valid <= '1';
        else
            output <= "00";
            valid <= '0';
        end if;
    end process;
end Behavioral;

-- Testbench to check the priority encoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_PriorityEncoder is
end tb_PriorityEncoder;

architecture Behavioral of tb_PriorityEncoder is
    signal inputs : std_logic_vector(3 downto 0);
    signal output : std_logic_vector(1 downto 0);
    signal valid : std_logic;
begin
    uut: entity work.PriorityEncoder
        port map(
            inputs => inputs,
            output => output,
            valid => valid
        );

    process
    begin
        inputs <= "0000"; wait for 10 ns;
        inputs <= "0001"; wait for 10 ns;
        inputs <= "0010"; wait for 10 ns;
        inputs <= "0100"; wait for 10 ns;
        inputs <= "1000"; wait for 10 ns;
        inputs <= "1010"; wait for 10 ns;
        wait;
    end process;
end Behavioral;

Important Notes

Make sure to check inputs from highest to lowest priority to get correct output.

The valid signal tells if any input is active.

Priority encoders are useful in hardware design to reduce complexity.

Summary

A priority encoder finds the highest priority active input.

It outputs a code showing which input is active first.

Useful in digital circuits and interrupt handling.