Priority encoder in VHDL

Introduction

A priority encoder helps find the highest priority input that is active. It turns many inputs into a smaller output code showing which input is the most important.

When you have multiple signals and want to know which one is active first.

In digital circuits to reduce many input lines to fewer output lines.

To decide which interrupt to handle first in a microcontroller.

When you want to encode the position of the first '1' in a set of bits.

Syntax

VHDL

entity PriorityEncoder is
    Port (
        inputs : in std_logic_vector(3 downto 0);
        output : out std_logic_vector(1 downto 0);
        valid : out std_logic
    );
end PriorityEncoder;

architecture Behavioral of PriorityEncoder is
begin
    process(inputs)
    begin
        if inputs(3) = '1' then
            output <= "11";
            valid <= '1';
        elsif inputs(2) = '1' then
            output <= "10";
            valid <= '1';
        elsif inputs(1) = '1' then
            output <= "01";
            valid <= '1';
        elsif inputs(0) = '1' then
            output <= "00";
            valid <= '1';
        else
            output <= "00";
            valid <= '0';
        end if;
    end process;
end Behavioral;

The inputs are checked from highest to lowest priority.

The output shows the position of the highest priority input that is '1'.

Examples

Checking inputs from highest bit 7 down to lower bits.

VHDL

if inputs(7) = '1' then
    output <= "111";
elsif inputs(6) = '1' then
    output <= "110";
-- and so on

Using case statement for fixed input patterns.

VHDL

process(inputs)
begin
    case inputs is
        when "1000" => output <= "11";
        when "0100" => output <= "10";
        when others => output <= "00";
    end case;
end process;

Sample Program

This program defines a priority encoder with 4 inputs. It outputs the position of the highest '1' bit and a valid signal. The testbench applies different inputs to see how the encoder responds.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity PriorityEncoder is
    Port (
        inputs : in std_logic_vector(3 downto 0);
        output : out std_logic_vector(1 downto 0);
        valid : out std_logic
    );
end PriorityEncoder;

architecture Behavioral of PriorityEncoder is
begin
    process(inputs)
    begin
        if inputs(3) = '1' then
            output <= "11";
            valid <= '1';
        elsif inputs(2) = '1' then
            output <= "10";
            valid <= '1';
        elsif inputs(1) = '1' then
            output <= "01";
            valid <= '1';
        elsif inputs(0) = '1' then
            output <= "00";
            valid <= '1';
        else
            output <= "00";
            valid <= '0';
        end if;
    end process;
end Behavioral;

-- Testbench to check the priority encoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_PriorityEncoder is
end tb_PriorityEncoder;

architecture Behavioral of tb_PriorityEncoder is
    signal inputs : std_logic_vector(3 downto 0);
    signal output : std_logic_vector(1 downto 0);
    signal valid : std_logic;
begin
    uut: entity work.PriorityEncoder
        port map(
            inputs => inputs,
            output => output,
            valid => valid
        );

    process
    begin
        inputs <= "0000"; wait for 10 ns;
        inputs <= "0001"; wait for 10 ns;
        inputs <= "0010"; wait for 10 ns;
        inputs <= "0100"; wait for 10 ns;
        inputs <= "1000"; wait for 10 ns;
        inputs <= "1010"; wait for 10 ns;
        wait;
    end process;
end Behavioral;

Important Notes

Make sure to check inputs from highest to lowest priority to get correct output.

The valid signal tells if any input is active.

Priority encoders are useful in hardware design to reduce complexity.

Summary

A priority encoder finds the highest priority active input.

It outputs a code showing which input is active first.

Useful in digital circuits and interrupt handling.

Practice

1.

What is the main function of a priority encoder in VHDL?

easy

A. It adds two binary numbers together.

B. It stores data temporarily.

C. It outputs the binary code of the highest priority active input.

D. It converts analog signals to digital.

Solution

1. Step 1: Understand the role of a priority encoder

   A priority encoder checks multiple inputs and finds the one with the highest priority that is active (usually '1').

2. Step 2: Identify the output behavior

   It outputs the binary code representing the position of that highest priority active input.

3. Final Answer:

   It outputs the binary code of the highest priority active input. -> Option C

4. Quick Check:

   Priority encoder = highest priority input code [OK]

Hint: Remember: priority encoder picks highest active input [OK]

Common Mistakes:

• Confusing priority encoder with adder
• Thinking it stores data like a register
• Mixing it up with analog-to-digital converter

2.

Which of the following is the correct VHDL syntax to declare a 4-to-2 priority encoder entity?

entity PriorityEncoder is
  Port (
    inputs : in std_logic_vector(3 downto 0);
    output : out std_logic_vector(1 downto 0)
  );
end PriorityEncoder;

easy

A. entity PriorityEncoder is
Port (
inputs : in std_logic_vector(3 downto 0);
output : out std_logic_vector(2 downto 0)
);
end PriorityEncoder;

B. entity PriorityEncoder is
Port (
inputs : in std_logic_vector(3 downto 0);
output : out std_logic_vector(1 downto 0)
);
end PriorityEncoder;

C. entity PriorityEncoder is
Port (
inputs : in std_logic_vector(0 to 3);
output : out std_logic_vector(1 downto 0)
);
end PriorityEncoder;

D. entity PriorityEncoder is
Port (
inputs : out std_logic_vector(3 downto 0);
output : in std_logic_vector(1 downto 0)
);
end PriorityEncoder;

Solution

1. Step 1: Check input and output directions

   Inputs should be in and outputs should be out. entity PriorityEncoder is Port ( inputs : in std_logic_vector(3 downto 0); output : out std_logic_vector(1 downto 0) ); end PriorityEncoder; correctly declares inputs as in and output as out.

2. Step 2: Verify vector ranges

   Inputs are 4 bits (3 downto 0) and output is 2 bits (1 downto 0), matching a 4-to-2 encoder. entity PriorityEncoder is Port ( inputs : in std_logic_vector(3 downto 0); output : out std_logic_vector(1 downto 0) ); end PriorityEncoder; matches this exactly.

3. Final Answer:

   Correct entity declaration with inputs as in and outputs as out, proper vector ranges. -> Option B

4. Quick Check:

   Input in, output out, correct vector sizes [OK]

Hint: Inputs are 'in', outputs are 'out' with correct vector sizes [OK]

Common Mistakes:

• Swapping input and output directions
• Using wrong vector ranges (e.g., 0 to 3 instead of 3 downto 0)
• Declaring output vector size incorrectly

3.

Given the following VHDL process for a 4-to-2 priority encoder, what will be the output when inputs = "0101"?

process(inputs)
begin
  case inputs is
    when "1000" => output <= "11";
    when "0100" => output <= "10";
    when "0010" => output <= "01";
    when "0001" => output <= "00";
    when others => output <= "00";
  end case;
end process;

medium

A. "00"

B. "11"

C. "01"

D. "10"

Solution

1. Step 1: Analyze the input pattern

   The input is "0101", which means bits 3 and 1 are active (bit 3 is MSB). The process checks exact matches only.

2. Step 2: Check case matches

   The case matches only exact inputs: "1000", "0100", "0010", "0001". "0101" does not match any, so it falls to when others.

3. Final Answer:

   Output is "00" from the when others clause. -> Option A

4. Quick Check:

   No exact match input = output "00" [OK]

Hint: Case matches exact inputs; else outputs default [OK]

Common Mistakes:

• Assuming partial matches trigger output
• Ignoring the when others clause
• Misreading input bit order

4.

Identify the error in this VHDL priority encoder process snippet:

process(inputs)
begin
  if inputs(0) = '1' then
    output <= "00";
  elsif inputs(1) = '1' then
    output <= "01";
  elsif inputs(2) = '1' then
    output <= "10";
  elsif inputs(3) = '1' then
    output <= "11";
  end if;
end process;

medium

A. The priority order is reversed; highest priority should be inputs(3).

B. The output vector size is incorrect.

C. The process is missing a sensitivity list.

D. The if-elsif structure should use case statement instead.

Solution

1. Step 1: Check priority order in conditions

   The process checks inputs starting from inputs(0) to inputs(3). This means input 0 has highest priority, which is usually incorrect for priority encoders.

2. Step 2: Understand typical priority encoder behavior

   Priority encoders usually assign highest priority to the highest index input (inputs(3) here). So the order should start checking inputs(3) first.

3. Final Answer:

   Priority order is reversed; highest priority should be inputs(3). -> Option A

4. Quick Check:

   Highest input bit checked first for priority [OK]

Hint: Check priority order: highest input bit first [OK]

Common Mistakes:

• Checking lowest bit first as highest priority
• Forgetting to include all inputs in conditions
• Confusing sensitivity list with process body

5.

You want to design a 8-to-3 priority encoder in VHDL that outputs the binary position of the highest priority input bit set to '1'. Which approach correctly implements this behavior?

process(inputs)
begin
  output <= "000";
  if inputs(7) = '1' then
    output <= "111";
  elsif inputs(6) = '1' then
    output <= "110";
  elsif inputs(5) = '1' then
    output <= "101";
  elsif inputs(4) = '1' then
    output <= "100";
  elsif inputs(3) = '1' then
    output <= "011";
  elsif inputs(2) = '1' then
    output <= "010";
  elsif inputs(1) = '1' then
    output <= "001";
  elsif inputs(0) = '1' then
    output <= "000";
  end if;
end process;

hard

A. This approach is incorrect; output should be assigned only once outside the process.

B. This approach is incorrect; it should use a case statement instead of if-elsif.

C. This approach is incorrect; inputs should be checked from lowest to highest.

D. This approach is correct; it checks inputs from highest to lowest and assigns output accordingly.

Solution

1. Step 1: Verify priority checking order

   The process checks inputs starting from inputs(7) down to inputs(0), which is correct for highest priority first.

2. Step 2: Confirm output assignment matches input position

   Output is assigned the binary code of the input bit position, matching the highest active input.

3. Step 3: Check default output assignment

   Output is initialized to "000" before checks, so if no inputs are active, output remains zero.

4. Final Answer:

   This approach is correct; it checks inputs from highest to lowest and assigns output accordingly. -> Option D

5. Quick Check:

   Highest to lowest check with matching output [OK]

Hint: Check inputs highest to lowest, assign output immediately [OK]

Common Mistakes:

• Checking inputs in wrong order
• Assigning output multiple times incorrectly
• Using case instead of if-elsif is optional, not required