Conditional assignment (when-else) in VHDL - Step-by-Step Execution

Concept Flow - Conditional assignment (when-else)

Evaluate condition1

Yes↓

Assign value1

↓

END

No↓

Evaluate condition2

Yes↓

Assign value2

↓

END

No↓

Assign default value

Check conditions in order; assign the value for the first true condition, else assign default.

Execution Sample

VHDL

output <= '1' when input = '1' else
          '0' when input = '0' else
          'Z';

Assign output based on input: '1' if input is '1', '0' if '0', else 'Z'.

Execution Table

Step	Condition Evaluated	Condition Result	Action Taken	Output Value
1	input = '1'	False	Check next condition	null
2	input = '0'	True	Assign '0' to output	'0'
3	No more conditions	N/A	End assignment	'0'

💡 Second condition true, output assigned '0', no further checks.

Variable Tracker

Variable	Start	After Step 1	After Step 2	Final
input	'0'	'0'	'0'	'0'
output	null	null	'0'	'0'

Key Moments - 2 Insights

Why does the output get '0' even though the first condition is checked first?

Because the first condition (input = '1') is false (see step 1 in execution_table), the code moves to the next condition and finds input = '0' true, so it assigns '0'.

What happens if none of the conditions are true?

The last else value is assigned as default ('Z' in this example), as shown in the concept_flow where after all conditions fail, the default assignment happens.

Visual Quiz - 3 Questions

Look at the execution_table, what is the output value after step 2?

A '0'

B '1'

C 'Z'

D null

💡 Hint

Check the 'Output Value' column at step 2 in execution_table.

At which step does the first condition evaluate to true?

A Step 1

B None

C Step 2

D Step 3

💡 Hint

Look at 'Condition Result' for step 1 in execution_table.

If input was '1', what would be the output value after step 1?

A 'Z'

B '0'

C '1'

D null

💡 Hint

Refer to the logic in concept_flow and how the first true condition assigns output.

Concept Snapshot

Syntax:
output <= value1 when condition1 else
          value2 when condition2 else
          default_value;

Behavior:
Checks conditions top-down, assigns value for first true condition.
If none true, assigns default_value.

Key rule:
Only one value assigned per evaluation, first true condition wins.

Full Transcript

This visual shows how VHDL conditional assignment with when-else works. The code checks each condition in order. If a condition is true, it assigns the corresponding value to the output and stops checking further. If no conditions are true, it assigns the default value after the last else. For example, if input is '0', the first condition input='1' is false, so it checks the second condition input='0' which is true, and assigns output '0'. Variables input and output change accordingly during execution. This step-by-step trace helps understand how conditional assignment picks the right value based on input.