Conditional assignment (when-else) in VHDL - Step-by-Step Execution

Concept Flow - Conditional assignment (when-else)

Evaluate condition1

Yes↓

Assign value1

↓

END

No↓

Evaluate condition2

Yes↓

Assign value2

↓

END

No↓

Assign default value

Check conditions in order; assign the value for the first true condition, else assign default.

Execution Sample

VHDL

output <= '1' when input = '1' else
          '0' when input = '0' else
          'Z';

Assign output based on input: '1' if input is '1', '0' if '0', else 'Z'.

Execution Table

Step	Condition Evaluated	Condition Result	Action Taken	Output Value
1	input = '1'	False	Check next condition	null
2	input = '0'	True	Assign '0' to output	'0'
3	No more conditions	N/A	End assignment	'0'

💡 Second condition true, output assigned '0', no further checks.

Variable Tracker

Variable	Start	After Step 1	After Step 2	Final
input	'0'	'0'	'0'	'0'
output	null	null	'0'	'0'

Key Moments - 2 Insights

Why does the output get '0' even though the first condition is checked first?

Because the first condition (input = '1') is false (see step 1 in execution_table), the code moves to the next condition and finds input = '0' true, so it assigns '0'.

What happens if none of the conditions are true?

The last else value is assigned as default ('Z' in this example), as shown in the concept_flow where after all conditions fail, the default assignment happens.

Visual Quiz - 3 Questions

Look at the execution_table, what is the output value after step 2?

A '0'

B '1'

C 'Z'

D null

💡 Hint

Check the 'Output Value' column at step 2 in execution_table.

At which step does the first condition evaluate to true?

A Step 1

B None

C Step 2

D Step 3

💡 Hint

Look at 'Condition Result' for step 1 in execution_table.

If input was '1', what would be the output value after step 1?

A 'Z'

B '0'

C '1'

D null

💡 Hint

Refer to the logic in concept_flow and how the first true condition assigns output.

Concept Snapshot

Syntax:
output <= value1 when condition1 else
          value2 when condition2 else
          default_value;

Behavior:
Checks conditions top-down, assigns value for first true condition.
If none true, assigns default_value.

Key rule:
Only one value assigned per evaluation, first true condition wins.

Full Transcript

This visual shows how VHDL conditional assignment with when-else works. The code checks each condition in order. If a condition is true, it assigns the corresponding value to the output and stops checking further. If no conditions are true, it assigns the default value after the last else. For example, if input is '0', the first condition input='1' is false, so it checks the second condition input='0' which is true, and assigns output '0'. Variables input and output change accordingly during execution. This step-by-step trace helps understand how conditional assignment picks the right value based on input.

Practice

1. What does the VHDL when-else statement do?

easy

A. Assigns a value to a signal based on a condition

B. Defines a loop to repeat actions

C. Declares a new signal type

D. Starts a process block

Solution

1. Step 1: Understand the purpose of when-else

   The when-else statement is used to assign values conditionally to signals in VHDL.

2. Step 2: Compare with other options

   Loops, signal declarations, and process blocks serve different purposes unrelated to conditional assignment.

3. Final Answer:

   Assigns a value to a signal based on a condition -> Option A

4. Quick Check:

   when-else = conditional assignment [OK]

Hint: Think of when-else as a quick if-else for signals [OK]

Common Mistakes:

• Confusing when-else with loops
• Thinking it declares signals
• Mixing it with process blocks

2. Which of the following is the correct syntax for a conditional assignment using when-else in VHDL?

easy

A. signal_name -> value1 when condition else value2;

B. signal_name <= value1 when condition else value2;

C. signal_name = value1 when condition else value2;

D. signal_name := value1 when condition else value2;

Solution

1. Step 1: Recall VHDL assignment operator

   In VHDL, signal assignment uses the '<=' operator, not ':=' or '='.

2. Step 2: Check the full syntax

   The correct syntax is: signal_name <= value1 when condition else value2;

3. Final Answer:

   signal_name <= value1 when condition else value2; -> Option B

4. Quick Check:

   Use '<=' for signal assignment with when-else [OK]

Hint: Use '<=' for signals, not ':=' or '=' [OK]

Common Mistakes:

• Using ':=' instead of '<=' for signals
• Using '=' which is for variables
• Confusing arrow operators

3. Given the VHDL code:

signal out_signal : std_logic;

out_signal <= '1' when input_signal = '1' else '0';

What will be the value of out_signal if input_signal is '0'?

medium

A. '0'

B. '1'

C. 'Z' (high impedance)

D. Undefined

Solution

1. Step 1: Analyze the condition

   The assignment says out_signal is '1' when input_signal = '1', else '0'.

2. Step 2: Apply input value

   Since input_signal is '0', the condition is false, so out_signal gets '0'.

3. Final Answer:

   '0' -> Option A

4. Quick Check:

   Condition false -> else value '0' assigned [OK]

Hint: If condition false, value after else is assigned [OK]

Common Mistakes:

• Assigning '1' when input is '0'
• Confusing high impedance 'Z' with '0'
• Thinking output is undefined

4. Identify the error in this VHDL conditional assignment:

signal result : std_logic;

result <= '1' when input = 1 else '0';

medium

A. Using '<=' instead of ':=' for assignment

B. Missing semicolon at the end

C. Signal name cannot be 'result'

D. Input comparison uses integer instead of character

Solution

1. Step 1: Check the condition type

   The input signal is likely std_logic, so it should be compared to a character like '1', not integer 1.

2. Step 2: Identify correct comparison

   Correct comparison is input = '1' (with single quotes) for std_logic.

3. Final Answer:

   Input comparison uses integer instead of character -> Option D

4. Quick Check:

   Compare std_logic with character '1' not integer 1 [OK]

Hint: Use single quotes for std_logic values in conditions [OK]

Common Mistakes:

• Comparing std_logic to integer without quotes
• Confusing assignment operators
• Assuming signal names are restricted

5. You want to assign a 4-bit output signal y based on a 2-bit input sel using conditional assignment. If sel is "00", assign "0001"; if "01", assign "0010"; else assign "0000". Which is the correct VHDL code?

hard

A. y := "0001" when sel = "00" else "0010" when sel = "01" else "0000";

B. y <= "0001" when sel = "00" else ("0010" when sel = "01" else "0000");

C. y <= "0001" when sel = "00" else "0010" when sel = "01" else "0000";

D. y <= '0001' when sel = "00" else '0010' when sel = "01" else '0000";

Solution

1. Step 1: Recall syntax for multiple conditions

   In VHDL, chain conditional assignments as: value1 when cond1 else value2 when cond2 else value3. No parentheses needed.

2. Step 2: Compare options

   y <= "0001" when sel = "00" else "0010" when sel = "01" else "0000"; matches the correct chained syntax.

3. Final Answer:

   y <= "0001" when sel = "00" else "0010" when sel = "01" else "0000"; -> Option C

4. Quick Check:

   Chained when-else without parentheses [OK]

Hint: Chain with else when, no parentheses needed [OK]

Common Mistakes:

• Using := for signal assignment
• Adding unnecessary parentheses around conditions
• Using single quotes for std_logic_vector literals