Conditional assignment (when-else) in VHDL - Time & Space Complexity

Time Complexity: Conditional assignment (when-else)

O(n)

Understanding Time Complexity

We want to understand how the time to run a conditional assignment in VHDL changes as inputs change.

Specifically, does the number of conditions affect how long it takes to decide the output?

Scenario Under Consideration

Analyze the time complexity of the following code snippet.

signal a, b, c, d : std_logic;
signal sel : std_logic_vector(1 downto 0);
signal out_signal : std_logic;

out_signal <= a when sel = "00" else
              b when sel = "01" else
              c when sel = "10" else
              d;
    

This code chooses one signal to assign to out_signal based on the value of sel.

Identify Repeating Operations

• Primary operation: Checking conditions in sequence to find a match.
• How many times: At most, it checks each condition once in order until one matches.

How Execution Grows With Input

As the number of conditions grows, the checks increase linearly.

Input Size (number of conditions)	Approx. Operations (condition checks)
2	Up to 2 checks
5	Up to 5 checks
10	Up to 10 checks

Pattern observation: The number of checks grows directly with the number of conditions.

Final Time Complexity

Time Complexity: O(n)

This means the time to decide the output grows in a straight line with the number of conditions.

Common Mistake

[X] Wrong: "The conditional assignment runs in constant time no matter how many conditions there are."

[OK] Correct: Because each condition is checked in order, more conditions mean more checks, so time grows with the number of conditions.

Interview Connect

Understanding how condition checks add up helps you reason about hardware design speed and efficiency, a useful skill in many design tasks.

Self-Check

"What if we replaced the when-else chain with a case statement? How would the time complexity change?"