Conditional assignment (when-else) in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a conditional assignment using when-else in VHDL?

It is a way to assign a value to a signal based on a condition. The syntax uses when to specify the condition and else for the default value.

beginner

Write the syntax of a simple conditional assignment using when-else in VHDL.

signal_name <= value1 when condition else value2;

This means if condition is true, assign value1, otherwise assign value2.

intermediate

Can you chain multiple conditions using when-else in VHDL?

Yes, you can chain multiple when-else statements to check several conditions in order. For example:

signal_name <= value1 when cond1 else value2 when cond2 else value3;

beginner

What happens if none of the conditions in a when-else chain are true?

The last else value is assigned as a default. This ensures the signal always gets a value.

intermediate

Why use when-else conditional assignment instead of an if statement in VHDL?

Because when-else is a concurrent statement, it can be used outside processes and is simpler for simple conditional assignments. if statements are sequential and used inside processes.

What does the following VHDL code do?

out_signal <= '1' when in_signal = '0' else '0';

A Assigns '1' to out_signal if in_signal is '0', else '0'

B Assigns '0' to out_signal if in_signal is '0', else '1'

C Assigns '1' to out_signal always

D Assigns '0' to out_signal always

The code assigns '1' to out_signal when in_signal equals '0'. Otherwise, it assigns '0'.

Which statement is true about when-else in VHDL?

A It is a concurrent statement used outside processes

B It cannot be chained for multiple conditions

C It is a sequential statement used inside processes

D It does not require an else clause

when-else is a concurrent statement and can be used outside processes.

How do you write a conditional assignment with multiple conditions in VHDL?

A Using nested if statements

B Using chained when-else statements

C Using case statements only

D Using loops

Multiple conditions can be handled by chaining when-else statements.

What is the default value in a when-else chain?

A The first value assigned

B There is no default value

C The value after the last else

D The value assigned if no conditions are true

The last else value acts as the default if no conditions match.

Which of these is a valid conditional assignment in VHDL?

A signal := '1' when condition else '0';

B signal <= '1' if condition else '0';

C signal <= '1' when condition else '0';

D signal = '1' when condition else '0';

The correct syntax uses <= with when-else for conditional assignment.

Explain how conditional assignment using when-else works in VHDL and give a simple example.

Think about assigning a signal based on a true or false condition.

Describe how to handle multiple conditions using when-else in VHDL and why the else part is important.

Consider what happens if none of the conditions are true.

Practice

1. What does the VHDL when-else statement do?

easy

A. Assigns a value to a signal based on a condition

B. Defines a loop to repeat actions

C. Declares a new signal type

D. Starts a process block

Solution

1. Step 1: Understand the purpose of when-else

   The when-else statement is used to assign values conditionally to signals in VHDL.

2. Step 2: Compare with other options

   Loops, signal declarations, and process blocks serve different purposes unrelated to conditional assignment.

3. Final Answer:

   Assigns a value to a signal based on a condition -> Option A

4. Quick Check:

   when-else = conditional assignment [OK]

Hint: Think of when-else as a quick if-else for signals [OK]

Common Mistakes:

• Confusing when-else with loops
• Thinking it declares signals
• Mixing it with process blocks

2. Which of the following is the correct syntax for a conditional assignment using when-else in VHDL?

easy

A. signal_name -> value1 when condition else value2;

B. signal_name <= value1 when condition else value2;

C. signal_name = value1 when condition else value2;

D. signal_name := value1 when condition else value2;

Solution

1. Step 1: Recall VHDL assignment operator

   In VHDL, signal assignment uses the '<=' operator, not ':=' or '='.

2. Step 2: Check the full syntax

   The correct syntax is: signal_name <= value1 when condition else value2;

3. Final Answer:

   signal_name <= value1 when condition else value2; -> Option B

4. Quick Check:

   Use '<=' for signal assignment with when-else [OK]

Hint: Use '<=' for signals, not ':=' or '=' [OK]

Common Mistakes:

• Using ':=' instead of '<=' for signals
• Using '=' which is for variables
• Confusing arrow operators

3. Given the VHDL code:

signal out_signal : std_logic;

out_signal <= '1' when input_signal = '1' else '0';

What will be the value of out_signal if input_signal is '0'?

medium

A. '0'

B. '1'

C. 'Z' (high impedance)

D. Undefined

Solution

1. Step 1: Analyze the condition

   The assignment says out_signal is '1' when input_signal = '1', else '0'.

2. Step 2: Apply input value

   Since input_signal is '0', the condition is false, so out_signal gets '0'.

3. Final Answer:

   '0' -> Option A

4. Quick Check:

   Condition false -> else value '0' assigned [OK]

Hint: If condition false, value after else is assigned [OK]

Common Mistakes:

• Assigning '1' when input is '0'
• Confusing high impedance 'Z' with '0'
• Thinking output is undefined

4. Identify the error in this VHDL conditional assignment:

signal result : std_logic;

result <= '1' when input = 1 else '0';

medium

A. Using '<=' instead of ':=' for assignment

B. Missing semicolon at the end

C. Signal name cannot be 'result'

D. Input comparison uses integer instead of character

Solution

1. Step 1: Check the condition type

   The input signal is likely std_logic, so it should be compared to a character like '1', not integer 1.

2. Step 2: Identify correct comparison

   Correct comparison is input = '1' (with single quotes) for std_logic.

3. Final Answer:

   Input comparison uses integer instead of character -> Option D

4. Quick Check:

   Compare std_logic with character '1' not integer 1 [OK]

Hint: Use single quotes for std_logic values in conditions [OK]

Common Mistakes:

• Comparing std_logic to integer without quotes
• Confusing assignment operators
• Assuming signal names are restricted

5. You want to assign a 4-bit output signal y based on a 2-bit input sel using conditional assignment. If sel is "00", assign "0001"; if "01", assign "0010"; else assign "0000". Which is the correct VHDL code?

hard

A. y := "0001" when sel = "00" else "0010" when sel = "01" else "0000";

B. y <= "0001" when sel = "00" else ("0010" when sel = "01" else "0000");

C. y <= "0001" when sel = "00" else "0010" when sel = "01" else "0000";

D. y <= '0001' when sel = "00" else '0010' when sel = "01" else '0000";

Solution

1. Step 1: Recall syntax for multiple conditions

   In VHDL, chain conditional assignments as: value1 when cond1 else value2 when cond2 else value3. No parentheses needed.

2. Step 2: Compare options

   y <= "0001" when sel = "00" else "0010" when sel = "01" else "0000"; matches the correct chained syntax.

3. Final Answer:

   y <= "0001" when sel = "00" else "0010" when sel = "01" else "0000"; -> Option C

4. Quick Check:

   Chained when-else without parentheses [OK]

Hint: Chain with else when, no parentheses needed [OK]

Common Mistakes:

• Using := for signal assignment
• Adding unnecessary parentheses around conditions
• Using single quotes for std_logic_vector literals