Conditional assignment (when-else) in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a conditional assignment using when-else in VHDL?

It is a way to assign a value to a signal based on a condition. The syntax uses when to specify the condition and else for the default value.

beginner

Write the syntax of a simple conditional assignment using when-else in VHDL.

signal_name <= value1 when condition else value2;

This means if condition is true, assign value1, otherwise assign value2.

intermediate

Can you chain multiple conditions using when-else in VHDL?

Yes, you can chain multiple when-else statements to check several conditions in order. For example:<br>

signal_name <= value1 when cond1 else value2 when cond2 else value3;

beginner

What happens if none of the conditions in a when-else chain are true?

The last else value is assigned as a default. This ensures the signal always gets a value.

intermediate

Why use when-else conditional assignment instead of an if statement in VHDL?

Because when-else is a concurrent statement, it can be used outside processes and is simpler for simple conditional assignments. if statements are sequential and used inside processes.

What does the following VHDL code do?<br>

out_signal <= '1' when in_signal = '0' else '0';

A Assigns '1' to out_signal if in_signal is '0', else '0'

B Assigns '0' to out_signal if in_signal is '0', else '1'

C Assigns '1' to out_signal always

D Assigns '0' to out_signal always

The code assigns '1' to out_signal when in_signal equals '0'. Otherwise, it assigns '0'.

Which statement is true about when-else in VHDL?

A It is a concurrent statement used outside processes

B It cannot be chained for multiple conditions

C It is a sequential statement used inside processes

D It does not require an else clause

when-else is a concurrent statement and can be used outside processes.

How do you write a conditional assignment with multiple conditions in VHDL?

A Using nested if statements

B Using chained when-else statements

C Using case statements only

D Using loops

Multiple conditions can be handled by chaining when-else statements.

What is the default value in a when-else chain?

A The first value assigned

B There is no default value

C The value after the last else

D The value assigned if no conditions are true

The last else value acts as the default if no conditions match.

Which of these is a valid conditional assignment in VHDL?

A signal := '1' when condition else '0';

B signal <= '1' if condition else '0';

C signal <= '1' when condition else '0';

D signal = '1' when condition else '0';

The correct syntax uses <= with when-else for conditional assignment.

Explain how conditional assignment using when-else works in VHDL and give a simple example.

Think about assigning a signal based on a true or false condition.

Describe how to handle multiple conditions using when-else in VHDL and why the else part is important.

Consider what happens if none of the conditions are true.