Conditional assignment (when-else) in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to assign '1' to signal 'out' when 'in' is '1', otherwise '0'.

VHDL

out <= '1' when in = [1] else '0';

Drag options to blanks, or click blank then click option'

A1

B"1"

C'0'

D'1'

Attempts:

3 left

💡 Hint

Common Mistakes

Using double quotes instead of single quotes for character literals.

Using numeric 1 without quotes.

In VHDL, single quotes denote a character literal. To check if signal 'in' equals '1', use 'in = '1''.

2fill in blank

medium

Complete the code to assign 'Z' to 'out' when 'enable' is '0', else assign '0'.

VHDL

out <= 'Z' when enable = [1] else '0';

Drag options to blanks, or click blank then click option'

A'0'

B'1'

C0

D1

Attempts:

3 left

💡 Hint

Common Mistakes

Using numeric 0 without quotes.

Using double quotes instead of single quotes.

To check if 'enable' is '0', use the character literal '0' with single quotes.

3fill in blank

hard

Fix the error in the conditional assignment to assign '1' when 'sel' is '1', else '0'.

VHDL

out <= '1' when sel [1] '1' else '0';

Drag options to blanks, or click blank then click option'

A==

B=

C:=

D=>

Attempts:

3 left

💡 Hint

Common Mistakes

Using '==' instead of '=' for comparison.

Using ':=' which is for assignment, not comparison.

In VHDL, the equality operator is '='. '==' is not valid syntax.

4fill in blank

hard

Fill both blanks to assign '1' when 'a' is '1' and 'b' is '0', else 'Z'.

VHDL

out <= '1' when a [1] '1' and b [2] '0' else 'Z';

Drag options to blanks, or click blank then click option'

A=

B==

C:=

D=>

Attempts:

3 left

💡 Hint

Common Mistakes

Using '==' or ':=' instead of '='.

Mixing assignment and comparison operators.

Use '=' for equality checks in VHDL conditions.

5fill in blank

hard

Fill all three blanks to assign '1' when 'x' is '1', 'y' is '0', and 'z' is '1', else '0'.

VHDL

out <= '1' when x [1] '1' and y [2] '0' and z [3] '1' else '0';

Drag options to blanks, or click blank then click option'

A==

B=

C:=

D=>

Attempts:

3 left

💡 Hint

Common Mistakes

Using '==' or ':=' instead of '='.

Confusing assignment with comparison operators.

All comparisons use '=' in VHDL for equality checks.