Conditional assignment (when-else) in VHDL - Mini Project: Build & Apply

Conditional Assignment with when-else in VHDL

📖 Scenario: You are designing a simple digital circuit that outputs a signal based on the value of a 2-bit input.This is like a traffic light controller that changes the light color depending on the input code.

🎯 Goal: Build a VHDL code snippet that uses when-else conditional assignment to set the output signal based on the input value.

📋 What You'll Learn

Create a 2-bit input signal called input_signal

Create a 1-bit output signal called output_signal

Use a when-else statement to assign output_signal as '1' when input_signal is "11"

Assign output_signal as '0' for all other input_signal values

💡 Why This Matters

🌍 Real World

Conditional assignments in VHDL are used to design hardware circuits that react differently based on input signals, like traffic lights or control units.

💼 Career

Understanding when-else conditional assignments is essential for FPGA and ASIC design engineers who write hardware description language code.

1

DATA SETUP: Declare input and output signals

Declare a 2-bit std_logic_vector signal called input_signal and a std_logic signal called output_signal inside the architecture.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_logic is
    Port (
        input_signal : in std_logic_vector(1 downto 0);
        output_signal : out std_logic
    );
end simple_logic;

architecture Behavioral of simple_logic is
begin
-- Your code here
end Behavioral;

Need a hint?

Remember to declare input_signal as a 2-bit vector and output_signal as a single bit signal in the entity port.

2

CONFIGURATION: Prepare for conditional assignment

Inside the architecture Behavioral, prepare to assign output_signal using a conditional assignment statement.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_logic is
    Port (
        input_signal : in std_logic_vector(1 downto 0);
        output_signal : out std_logic
    );
end simple_logic;

architecture Behavioral of simple_logic is
begin
-- Prepare for conditional assignment of output_signal

end Behavioral;

Need a hint?

Make sure you are inside the architecture Behavioral block to write the conditional assignment.

3

CORE LOGIC: Use when-else conditional assignment

Write a conditional assignment for output_signal using when-else so that output_signal is '1' when input_signal equals "11", and '0' otherwise.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_logic is
    Port (
        input_signal : in std_logic_vector(1 downto 0);
        output_signal : out std_logic
    );
end simple_logic;

architecture Behavioral of simple_logic is
begin
-- Assign output_signal using when-else

end Behavioral;

Need a hint?

Use the syntax: output_signal <= '1' when input_signal = "11" else '0';

4

OUTPUT: Display the conditional assignment result

Print the VHDL code line that assigns output_signal using when-else.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_logic is
    Port (
        input_signal : in std_logic_vector(1 downto 0);
        output_signal : out std_logic
    );
end simple_logic;

architecture Behavioral of simple_logic is
begin
    output_signal <= '1' when input_signal = "11" else '0';

-- Print the conditional assignment line below

Need a hint?

Use the report statement to print the conditional assignment line.