Conditional assignment (when-else) in VHDL - Mini Project: Build & Apply

Conditional Assignment with when-else in VHDL

📖 Scenario: You are designing a simple digital circuit that outputs a signal based on the value of a 2-bit input.This is like a traffic light controller that changes the light color depending on the input code.

🎯 Goal: Build a VHDL code snippet that uses when-else conditional assignment to set the output signal based on the input value.

📋 What You'll Learn

Create a 2-bit input signal called input_signal

Create a 1-bit output signal called output_signal

Use a when-else statement to assign output_signal as '1' when input_signal is "11"

Assign output_signal as '0' for all other input_signal values

💡 Why This Matters

🌍 Real World

Conditional assignments in VHDL are used to design hardware circuits that react differently based on input signals, like traffic lights or control units.

💼 Career

Understanding when-else conditional assignments is essential for FPGA and ASIC design engineers who write hardware description language code.

1

DATA SETUP: Declare input and output signals

Declare a 2-bit std_logic_vector signal called input_signal and a std_logic signal called output_signal inside the architecture.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_logic is
    Port (
        input_signal : in std_logic_vector(1 downto 0);
        output_signal : out std_logic
    );
end simple_logic;

architecture Behavioral of simple_logic is
begin
-- Your code here
end Behavioral;

Hint

Remember to declare input_signal as a 2-bit vector and output_signal as a single bit signal in the entity port.

2

CONFIGURATION: Prepare for conditional assignment

Inside the architecture Behavioral, prepare to assign output_signal using a conditional assignment statement.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_logic is
    Port (
        input_signal : in std_logic_vector(1 downto 0);
        output_signal : out std_logic
    );
end simple_logic;

architecture Behavioral of simple_logic is
begin
-- Prepare for conditional assignment of output_signal

end Behavioral;

Hint

Make sure you are inside the architecture Behavioral block to write the conditional assignment.

3

CORE LOGIC: Use when-else conditional assignment

Write a conditional assignment for output_signal using when-else so that output_signal is '1' when input_signal equals "11", and '0' otherwise.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_logic is
    Port (
        input_signal : in std_logic_vector(1 downto 0);
        output_signal : out std_logic
    );
end simple_logic;

architecture Behavioral of simple_logic is
begin
-- Assign output_signal using when-else

end Behavioral;

Hint

Use the syntax: output_signal <= '1' when input_signal = "11" else '0';

4

OUTPUT: Display the conditional assignment result

Print the VHDL code line that assigns output_signal using when-else.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_logic is
    Port (
        input_signal : in std_logic_vector(1 downto 0);
        output_signal : out std_logic
    );
end simple_logic;

architecture Behavioral of simple_logic is
begin
    output_signal <= '1' when input_signal = "11" else '0';

-- Print the conditional assignment line below

Hint

Use the report statement to print the conditional assignment line.

Practice

1. What does the VHDL when-else statement do?

easy

A. Assigns a value to a signal based on a condition

B. Defines a loop to repeat actions

C. Declares a new signal type

D. Starts a process block

Solution

1. Step 1: Understand the purpose of when-else

   The when-else statement is used to assign values conditionally to signals in VHDL.

2. Step 2: Compare with other options

   Loops, signal declarations, and process blocks serve different purposes unrelated to conditional assignment.

3. Final Answer:

   Assigns a value to a signal based on a condition -> Option A

4. Quick Check:

   when-else = conditional assignment [OK]

Hint: Think of when-else as a quick if-else for signals [OK]

Common Mistakes:

• Confusing when-else with loops
• Thinking it declares signals
• Mixing it with process blocks

2. Which of the following is the correct syntax for a conditional assignment using when-else in VHDL?

easy

A. signal_name -> value1 when condition else value2;

B. signal_name <= value1 when condition else value2;

C. signal_name = value1 when condition else value2;

D. signal_name := value1 when condition else value2;

Solution

1. Step 1: Recall VHDL assignment operator

   In VHDL, signal assignment uses the '<=' operator, not ':=' or '='.

2. Step 2: Check the full syntax

   The correct syntax is: signal_name <= value1 when condition else value2;

3. Final Answer:

   signal_name <= value1 when condition else value2; -> Option B

4. Quick Check:

   Use '<=' for signal assignment with when-else [OK]

Hint: Use '<=' for signals, not ':=' or '=' [OK]

Common Mistakes:

• Using ':=' instead of '<=' for signals
• Using '=' which is for variables
• Confusing arrow operators

3. Given the VHDL code:

signal out_signal : std_logic;

out_signal <= '1' when input_signal = '1' else '0';

What will be the value of out_signal if input_signal is '0'?

medium

A. '0'

B. '1'

C. 'Z' (high impedance)

D. Undefined

Solution

1. Step 1: Analyze the condition

   The assignment says out_signal is '1' when input_signal = '1', else '0'.

2. Step 2: Apply input value

   Since input_signal is '0', the condition is false, so out_signal gets '0'.

3. Final Answer:

   '0' -> Option A

4. Quick Check:

   Condition false -> else value '0' assigned [OK]

Hint: If condition false, value after else is assigned [OK]

Common Mistakes:

• Assigning '1' when input is '0'
• Confusing high impedance 'Z' with '0'
• Thinking output is undefined

4. Identify the error in this VHDL conditional assignment:

signal result : std_logic;

result <= '1' when input = 1 else '0';

medium

A. Using '<=' instead of ':=' for assignment

B. Missing semicolon at the end

C. Signal name cannot be 'result'

D. Input comparison uses integer instead of character

Solution

1. Step 1: Check the condition type

   The input signal is likely std_logic, so it should be compared to a character like '1', not integer 1.

2. Step 2: Identify correct comparison

   Correct comparison is input = '1' (with single quotes) for std_logic.

3. Final Answer:

   Input comparison uses integer instead of character -> Option D

4. Quick Check:

   Compare std_logic with character '1' not integer 1 [OK]

Hint: Use single quotes for std_logic values in conditions [OK]

Common Mistakes:

• Comparing std_logic to integer without quotes
• Confusing assignment operators
• Assuming signal names are restricted

5. You want to assign a 4-bit output signal y based on a 2-bit input sel using conditional assignment. If sel is "00", assign "0001"; if "01", assign "0010"; else assign "0000". Which is the correct VHDL code?

hard

A. y := "0001" when sel = "00" else "0010" when sel = "01" else "0000";

B. y <= "0001" when sel = "00" else ("0010" when sel = "01" else "0000");

C. y <= "0001" when sel = "00" else "0010" when sel = "01" else "0000";

D. y <= '0001' when sel = "00" else '0010' when sel = "01" else '0000";

Solution

1. Step 1: Recall syntax for multiple conditions

   In VHDL, chain conditional assignments as: value1 when cond1 else value2 when cond2 else value3. No parentheses needed.

2. Step 2: Compare options

   y <= "0001" when sel = "00" else "0010" when sel = "01" else "0000"; matches the correct chained syntax.

3. Final Answer:

   y <= "0001" when sel = "00" else "0010" when sel = "01" else "0000"; -> Option C

4. Quick Check:

   Chained when-else without parentheses [OK]

Hint: Chain with else when, no parentheses needed [OK]

Common Mistakes:

• Using := for signal assignment
• Adding unnecessary parentheses around conditions
• Using single quotes for std_logic_vector literals