Conditional assignment (when-else) in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this VHDL conditional assignment?

Given the following VHDL code snippet, what is the value of y when a = '1' and b = '0'?

VHDL

y <= '1' when a = '1' else '0';

A '1'

B '0'

C 'Z'

D 'X'

💡 Hint

Remember, the conditional assignment sets y to '1' only if a is '1'.

The conditional assignment sets y to '1' when a = '1'. Since a is '1', y becomes '1'.

❓ Predict Output

intermediate

What value does out_signal get with multiple conditions?

Consider this VHDL code:

out_signal <= '1' when sel = "00" else
              '0' when sel = "01" else
              'Z';

What is the value of out_signal when sel = "01"?

VHDL

out_signal <= '1' when sel = "00" else
              '0' when sel = "01" else
              'Z';

A '1'

B 'Z'

C '0'

D 'X'

💡 Hint

Check the order of conditions and which matches sel.

The second condition matches sel = "01", so out_signal is assigned '0'.

🔧 Debug

advanced

Identify the error in this conditional assignment

What error will this VHDL code produce?

signal x : std_logic;
x <= '1' when a = '1' else '0' when b = '1';

VHDL

x <= '1' when a = '1' else '0' when b = '1';

A Syntax error: missing final else clause

B Runtime error: signal conflict

C No error, code runs correctly

D Type mismatch error

💡 Hint

Check if all possible conditions are covered with else clauses.

The conditional assignment must end with a final else clause to cover all cases. This code misses that, causing a syntax error.

❓ Predict Output

advanced

What is the output of nested conditional assignments?

Given this VHDL code:

y <= '1' when (a = '1' and b = '0') else
     '0' when (a = '0' and b = '1') else
     'Z';

What is the value of y when a = '0' and b = '0'?

VHDL

y <= '1' when (a = '1' and b = '0') else
     '0' when (a = '0' and b = '1') else
     'Z';

A '1'

B 'Z'

C '0'

D 'X'

💡 Hint

Neither condition matches, so the final else applies.

Since neither condition is true for a = '0' and b = '0', the final else clause assigns 'Z'.

🧠 Conceptual

expert

How many items are in the resulting signal assignment?

Consider this VHDL conditional assignment:

signal s : std_logic_vector(3 downto 0);
s <= "0001" when cond1 else
     "0010" when cond2 else
     "0100" when cond3 else
     "1000";

How many distinct possible values can s have based on the conditions?

A 1

B 3

C 2

D 4

💡 Hint

Count each unique assignment including the final else.

There are four possible values: one for each condition cond1, cond2, cond3, and the final else clause.