Concurrent signal assignment in VHDL - Step-by-Step Execution

Concept Flow - Concurrent signal assignment

Start

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Evaluate RHS expression

↓

Assign value to signal

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Signal updates concurrently

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Wait for next event or delta cycle

↩Back to Evaluate RHS expression

Concurrent signal assignment continuously evaluates the right side and updates the signal in parallel with other processes.

Execution Sample

VHDL

signal a, b, c : std_logic;

c <= a and b;

-- When a or b changes, c updates concurrently

Assigns signal c as the AND of signals a and b concurrently.

Execution Table

Step	Signal a	Signal b	Evaluate RHS (a and b)	Assign to c	Signal c value
1	'0'	'0'	'0' and '0' = '0'	c <= '0'	'0'
2	'1' (a changes)	'0'	'1' and '0' = '0'	c <= '0'	'0'
3	'1'	'1' (b changes)	'1' and '1' = '1'	c <= '1'	'1'
4	'0' (a changes)	'1'	'0' and '1' = '0'	c <= '0'	'0'
5	'0'	'0' (b changes)	'0' and '0' = '0'	c <= '0'	'0'
6	No changes	No changes	No re-evaluation	No assignment	'0'

💡 No signal changes, so no further concurrent assignments occur.

Variable Tracker

Signal	Start	After 1	After 2	After 3	After 4	After 5	Final
a	'0'	'0'	'1'	'1'	'0'	'0'	'0'
b	'0'	'0'	'0'	'1'	'1'	'0'	'0'
c	'0'	'0'	'0'	'1'	'0'	'0'	'0'

Key Moments - 3 Insights

Why does signal c update immediately when a or b changes?

Because concurrent signal assignment continuously monitors signals a and b, any change triggers re-evaluation and updates c as shown in steps 2 and 3 in the execution_table.

Does the assignment to c happen in order or all at once?

All concurrent assignments happen in parallel, so c updates independently whenever its inputs change, not waiting for other signals.

Why does the signal c not change when a and b stay the same?

Because concurrent assignment only triggers when input signals change; if a and b remain constant, no re-evaluation or assignment occurs (step 6).

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of signal c after step 3?

A '1'

B 'X' (unknown)

C '0'

D 'Z' (high impedance)

💡 Hint

Check the 'Signal c value' column at step 3 in the execution_table.

At which step does signal a change from '1' to '0'?

A Step 2

B Step 3

C Step 4

D Step 5

💡 Hint

Look at the 'Signal a' column in the execution_table to find when it changes to '0'.

If signal b never changes from '0', what would be the value of c after step 1?

A '1'

B '0'

C No value assigned

D 'Z'

💡 Hint

Refer to the logic 'a and b' in the execution_table and variable_tracker.

Concept Snapshot

Concurrent signal assignment in VHDL:
- Syntax: signal_name <= expression;
- Continuously evaluates RHS when inputs change.
- Updates signal value concurrently with other assignments.
- No order; all assignments happen in parallel.
- Signal updates only on input changes.

Full Transcript

Concurrent signal assignment in VHDL means the signal on the left side is updated whenever any signal on the right side changes. The process runs in parallel with other concurrent statements. For example, if c <= a and b; then whenever a or b changes, c is recalculated and updated. This happens immediately and independently of other signals. The execution table shows how signals a and b change step by step and how c updates accordingly. If no inputs change, the signal c remains the same and no new assignment occurs. This helps hardware describe circuits that react instantly to input changes.