Concurrent signal assignment in VHDL - Step-by-Step Execution

Concept Flow - Concurrent signal assignment

Start

↓

Evaluate RHS expression

↓

Assign value to signal

↓

Signal updates concurrently

↓

Wait for next event or delta cycle

↩Back to Evaluate RHS expression

Concurrent signal assignment continuously evaluates the right side and updates the signal in parallel with other processes.

Execution Sample

VHDL

signal a, b, c : std_logic;

c <= a and b;

-- When a or b changes, c updates concurrently

Assigns signal c as the AND of signals a and b concurrently.

Execution Table

Step	Signal a	Signal b	Evaluate RHS (a and b)	Assign to c	Signal c value
1	'0'	'0'	'0' and '0' = '0'	c <= '0'	'0'
2	'1' (a changes)	'0'	'1' and '0' = '0'	c <= '0'	'0'
3	'1'	'1' (b changes)	'1' and '1' = '1'	c <= '1'	'1'
4	'0' (a changes)	'1'	'0' and '1' = '0'	c <= '0'	'0'
5	'0'	'0' (b changes)	'0' and '0' = '0'	c <= '0'	'0'
6	No changes	No changes	No re-evaluation	No assignment	'0'

💡 No signal changes, so no further concurrent assignments occur.

Variable Tracker

Signal	Start	After 1	After 2	After 3	After 4	After 5	Final
a	'0'	'0'	'1'	'1'	'0'	'0'	'0'
b	'0'	'0'	'0'	'1'	'1'	'0'	'0'
c	'0'	'0'	'0'	'1'	'0'	'0'	'0'

Key Moments - 3 Insights

Why does signal c update immediately when a or b changes?

Because concurrent signal assignment continuously monitors signals a and b, any change triggers re-evaluation and updates c as shown in steps 2 and 3 in the execution_table.

Does the assignment to c happen in order or all at once?

All concurrent assignments happen in parallel, so c updates independently whenever its inputs change, not waiting for other signals.

Why does the signal c not change when a and b stay the same?

Because concurrent assignment only triggers when input signals change; if a and b remain constant, no re-evaluation or assignment occurs (step 6).

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of signal c after step 3?

A '1'

B 'X' (unknown)

C '0'

D 'Z' (high impedance)

💡 Hint

Check the 'Signal c value' column at step 3 in the execution_table.

At which step does signal a change from '1' to '0'?

A Step 2

B Step 3

C Step 4

D Step 5

💡 Hint

Look at the 'Signal a' column in the execution_table to find when it changes to '0'.

If signal b never changes from '0', what would be the value of c after step 1?

A '1'

B '0'

C No value assigned

D 'Z'

💡 Hint

Refer to the logic 'a and b' in the execution_table and variable_tracker.

Concept Snapshot

Concurrent signal assignment in VHDL:
- Syntax: signal_name <= expression;
- Continuously evaluates RHS when inputs change.
- Updates signal value concurrently with other assignments.
- No order; all assignments happen in parallel.
- Signal updates only on input changes.

Full Transcript

Concurrent signal assignment in VHDL means the signal on the left side is updated whenever any signal on the right side changes. The process runs in parallel with other concurrent statements. For example, if c <= a and b; then whenever a or b changes, c is recalculated and updated. This happens immediately and independently of other signals. The execution table shows how signals a and b change step by step and how c updates accordingly. If no inputs change, the signal c remains the same and no new assignment occurs. This helps hardware describe circuits that react instantly to input changes.

Practice

1. What does a concurrent signal assignment in VHDL do?
signal_name <= expression;

easy

A. Continuously updates the signal with the expression value in parallel

B. Executes the assignment only once at the start

C. Assigns the signal value sequentially after a delay

D. Creates a variable instead of a signal

Solution

1. Step 1: Understand concurrent assignment meaning

   Concurrent signal assignment updates the signal continuously and in parallel with other concurrent statements.

2. Step 2: Compare with other options

   Options B and C describe sequential or one-time behavior, which is incorrect. Creates a variable instead of a signal confuses signals with variables.

3. Final Answer:

   Continuously updates the signal with the expression value in parallel -> Option A

4. Quick Check:

   Concurrent assignment = continuous parallel update [OK]

Hint: Concurrent means always active and parallel [OK]

Common Mistakes:

• Thinking assignment happens only once
• Confusing signals with variables
• Assuming sequential execution

2. Which of the following is the correct syntax for a concurrent signal assignment in VHDL?

easy

A. signal_name <= expression;

B. signal_name = expression;

C. signal_name := expression;

D. signal_name -> expression;

Solution

1. Step 1: Recall VHDL signal assignment syntax

   In VHDL, concurrent signal assignment uses the "<=" operator.

2. Step 2: Eliminate incorrect options

   signal_name := expression; uses ":=", which is for variables, not signals. signal_name = expression; uses "=", which is not valid for signal assignment. signal_name -> expression; uses "->", which is invalid syntax.

3. Final Answer:

   signal_name <= expression; -> Option A

4. Quick Check:

   Signal assignment operator = <= [OK]

Hint: Use <= for signals, := for variables [OK]

Common Mistakes:

• Using := instead of <=
• Using = for signal assignment
• Confusing signal and variable syntax

3. Given the following VHDL code snippet:

signal a, b, c : std_logic;
b <= '1';
c <= b;
a <= c;

What is the value of signal a after simulation stabilizes?

medium

A. '0'

B. '1'

C. 'U' (uninitialized)

D. Simulation error

Solution

1. Step 1: Trace signal assignments

   b is assigned '1' concurrently, so b = '1'. Then c <= b means c = '1'. Then a <= c means a = '1'.

2. Step 2: Understand concurrent updates

   All assignments happen in parallel, so signals propagate the value '1' through b, c, and a.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   Signal chain propagates '1' [OK]

Hint: Follow signal chain step-by-step [OK]

Common Mistakes:

• Assuming initial 'U' remains
• Thinking assignments happen sequentially
• Confusing signal and variable updates

4. Identify the error in this VHDL concurrent signal assignment:

signal x : std_logic;
x = '1';

medium

A. Signal x must be declared as variable

B. Missing semicolon after signal declaration

C. Using '=' instead of '<=' for signal assignment

D. Signal cannot be assigned a constant

Solution

1. Step 1: Check assignment operator

   In VHDL, signals use '<=' for assignment, not '='.

2. Step 2: Verify other syntax

   Semicolon is present after declaration. Signal can be assigned constants. No need to declare as variable.

3. Final Answer:

   Using '=' instead of '<=' for signal assignment -> Option C

4. Quick Check:

   Signal assignment uses <= [OK]

Hint: Signals use <=, variables use := [OK]

Common Mistakes:

• Using = instead of <=
• Confusing signals with variables
• Thinking signals can't hold constants

5. You want to create a 2-bit signal out_sig that is always the bitwise AND of two 2-bit input signals in1 and in2. Which concurrent signal assignment correctly implements this?

hard

A. out_sig <= in1 & in2;

B. out_sig <= in1 or in2;

C. out_sig := in1 and in2;

D. out_sig <= in1 and in2;

Solution

1. Step 1: Identify correct operator for bitwise AND

   In VHDL, 'and' is the bitwise AND operator for std_logic_vector signals.

2. Step 2: Check syntax and operators

   out_sig <= in1 and in2; uses 'and' with '<=' which is correct. out_sig <= in1 & in2; uses '&' which is concatenation, not AND. out_sig := in1 and in2; uses ':=' which is for variables, not signals. out_sig <= in1 or in2; uses 'or' which is incorrect logic.

3. Final Answer:

   out_sig <= in1 and in2; -> Option D

4. Quick Check:

   Bitwise AND uses 'and' with <= [OK]

Hint: Use 'and' for bitwise AND, not '&' [OK]

Common Mistakes:

• Using '&' instead of 'and' for bitwise AND
• Using := instead of <=
• Using wrong logic operator