Concurrent signal assignment in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a concurrent signal assignment in VHDL?

A concurrent signal assignment is a statement that assigns a value to a signal and is evaluated continuously in parallel with other concurrent statements.

beginner

How does a concurrent signal assignment differ from a sequential assignment in VHDL?

Concurrent assignments run in parallel and outside processes, while sequential assignments run inside processes and execute step-by-step.

beginner

Example of a simple concurrent signal assignment in VHDL?

Example:
output_signal <= input_signal1 AND input_signal2;
This continuously updates output_signal based on inputs.

intermediate

Can concurrent signal assignments use conditional expressions?

Yes, concurrent signal assignments can use conditional expressions like 'when-else' or 'with-select' to assign values based on conditions.

intermediate

What happens if multiple concurrent assignments drive the same signal?

If multiple concurrent assignments drive the same signal, it causes a conflict or multiple drivers error unless resolved by resolved signal types.

Which statement best describes concurrent signal assignment in VHDL?

A It executes statements one after another inside a process.

B It continuously updates a signal in parallel with other statements.

C It only runs once at the start of simulation.

D It assigns values to variables, not signals.

Concurrent signal assignments run in parallel and continuously update signals.

Where are concurrent signal assignments placed in VHDL code?

A Outside any process block.

B Inside a process block.

C Only inside functions.

D Inside packages.

Concurrent signal assignments are placed outside processes to run in parallel.

What keyword is used for conditional concurrent signal assignment?

A case

B if-then

C loop

D when-else

'when-else' is used for conditional concurrent signal assignments.

What type of signal can resolve conflicts from multiple concurrent drivers?

A Resolved signal type

B Integer signal

C Variable

D Constant

Resolved signal types handle multiple drivers by defining resolution functions.

Which of these is NOT true about concurrent signal assignments?

A They can use conditional expressions.

B They update signals continuously.

C They execute sequentially inside a process.

D They run in parallel with other concurrent statements.

Concurrent assignments do not execute sequentially inside a process; that describes sequential assignments.

Explain what a concurrent signal assignment is and how it works in VHDL.

Think about how signals change in hardware circuits continuously.

Describe the difference between concurrent and sequential signal assignments in VHDL.

Consider where each type of assignment is written and how it behaves during simulation.

Practice

1. What does a concurrent signal assignment in VHDL do?
signal_name <= expression;

easy

A. Continuously updates the signal with the expression value in parallel

B. Executes the assignment only once at the start

C. Assigns the signal value sequentially after a delay

D. Creates a variable instead of a signal

Solution

1. Step 1: Understand concurrent assignment meaning

   Concurrent signal assignment updates the signal continuously and in parallel with other concurrent statements.

2. Step 2: Compare with other options

   Options B and C describe sequential or one-time behavior, which is incorrect. Creates a variable instead of a signal confuses signals with variables.

3. Final Answer:

   Continuously updates the signal with the expression value in parallel -> Option A

4. Quick Check:

   Concurrent assignment = continuous parallel update [OK]

Hint: Concurrent means always active and parallel [OK]

Common Mistakes:

• Thinking assignment happens only once
• Confusing signals with variables
• Assuming sequential execution

2. Which of the following is the correct syntax for a concurrent signal assignment in VHDL?

easy

A. signal_name <= expression;

B. signal_name = expression;

C. signal_name := expression;

D. signal_name -> expression;

Solution

1. Step 1: Recall VHDL signal assignment syntax

   In VHDL, concurrent signal assignment uses the "<=" operator.

2. Step 2: Eliminate incorrect options

   signal_name := expression; uses ":=", which is for variables, not signals. signal_name = expression; uses "=", which is not valid for signal assignment. signal_name -> expression; uses "->", which is invalid syntax.

3. Final Answer:

   signal_name <= expression; -> Option A

4. Quick Check:

   Signal assignment operator = <= [OK]

Hint: Use <= for signals, := for variables [OK]

Common Mistakes:

• Using := instead of <=
• Using = for signal assignment
• Confusing signal and variable syntax

3. Given the following VHDL code snippet:

signal a, b, c : std_logic;
b <= '1';
c <= b;
a <= c;

What is the value of signal a after simulation stabilizes?

medium

A. '0'

B. '1'

C. 'U' (uninitialized)

D. Simulation error

Solution

1. Step 1: Trace signal assignments

   b is assigned '1' concurrently, so b = '1'. Then c <= b means c = '1'. Then a <= c means a = '1'.

2. Step 2: Understand concurrent updates

   All assignments happen in parallel, so signals propagate the value '1' through b, c, and a.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   Signal chain propagates '1' [OK]

Hint: Follow signal chain step-by-step [OK]

Common Mistakes:

• Assuming initial 'U' remains
• Thinking assignments happen sequentially
• Confusing signal and variable updates

4. Identify the error in this VHDL concurrent signal assignment:

signal x : std_logic;
x = '1';

medium

A. Signal x must be declared as variable

B. Missing semicolon after signal declaration

C. Using '=' instead of '<=' for signal assignment

D. Signal cannot be assigned a constant

Solution

1. Step 1: Check assignment operator

   In VHDL, signals use '<=' for assignment, not '='.

2. Step 2: Verify other syntax

   Semicolon is present after declaration. Signal can be assigned constants. No need to declare as variable.

3. Final Answer:

   Using '=' instead of '<=' for signal assignment -> Option C

4. Quick Check:

   Signal assignment uses <= [OK]

Hint: Signals use <=, variables use := [OK]

Common Mistakes:

• Using = instead of <=
• Confusing signals with variables
• Thinking signals can't hold constants

5. You want to create a 2-bit signal out_sig that is always the bitwise AND of two 2-bit input signals in1 and in2. Which concurrent signal assignment correctly implements this?

hard

A. out_sig <= in1 & in2;

B. out_sig <= in1 or in2;

C. out_sig := in1 and in2;

D. out_sig <= in1 and in2;

Solution

1. Step 1: Identify correct operator for bitwise AND

   In VHDL, 'and' is the bitwise AND operator for std_logic_vector signals.

2. Step 2: Check syntax and operators

   out_sig <= in1 and in2; uses 'and' with '<=' which is correct. out_sig <= in1 & in2; uses '&' which is concatenation, not AND. out_sig := in1 and in2; uses ':=' which is for variables, not signals. out_sig <= in1 or in2; uses 'or' which is incorrect logic.

3. Final Answer:

   out_sig <= in1 and in2; -> Option D

4. Quick Check:

   Bitwise AND uses 'and' with <= [OK]

Hint: Use 'and' for bitwise AND, not '&' [OK]

Common Mistakes:

• Using '&' instead of 'and' for bitwise AND
• Using := instead of <=
• Using wrong logic operator