Concurrent signal assignment in VHDL - Deep Dive

Overview - Concurrent signal assignment

What is it?

Concurrent signal assignment in VHDL is a way to describe how signals change in hardware designs. It means assigning values to signals that happen all the time, not step-by-step like in a program. These assignments run in parallel, reflecting how real circuits work simultaneously. This helps model hardware behavior accurately.

Why it matters

Without concurrent signal assignment, we couldn't describe hardware circuits properly because hardware parts work at the same time, not one after another. If we tried to use only step-by-step instructions, the design would be slow and incorrect. Concurrent assignments let us write code that matches real electronic circuits, making designs reliable and efficient.

Where it fits

Before learning concurrent signal assignment, you should understand basic VHDL syntax and what signals are. After this, you can learn about processes and sequential statements, which describe step-by-step behavior inside hardware blocks.

Mental Model

Core Idea

Concurrent signal assignment lets you describe hardware signals changing in parallel, just like real circuits do.

Think of it like...

Imagine a group of friends all turning their lights on or off independently at the same time, rather than waiting for one friend to finish before the next starts. Concurrent signal assignment is like each friend controlling their light switch simultaneously.

┌─────────────────────────────┐
│ Concurrent Signal Assignment │
├───────────────┬─────────────┤
│ Signal A <= X │ Signal B <= Y│
│ (runs in     │ (runs in    │
│ parallel)    │ parallel)   │
└───────────────┴─────────────┘

Build-Up - 7 Steps

1

Foundation

Understanding signals in VHDL

Concept: Signals represent wires or connections in hardware that carry values.

In VHDL, signals are like wires that carry data between components. You declare signals and assign values to them. Unlike variables in software, signals update their values after some delay, reflecting real hardware behavior.

Result

You can represent hardware connections and data flow using signals.

Knowing signals are like wires helps you think in hardware terms, not software variables.

2

Foundation

Basic concurrent assignment syntax

Concept: Concurrent signal assignment uses the '<=' operator outside processes to assign values continuously.

Example: signal_a <= '1'; signal_b <= signal_a; These assignments happen all the time, not in order. The value of signal_b depends on signal_a's current value.

Result

Signals update automatically whenever their inputs change.

Understanding that assignments happen continuously helps you model hardware that reacts instantly.

3

Intermediate

Using expressions in concurrent assignments

Concept: You can assign signals using expressions combining other signals and operators.

Example: signal_c <= signal_a AND signal_b; This means signal_c is always the result of ANDing signal_a and signal_b. If either input changes, signal_c updates automatically.

Result

Signal_c reflects the logical AND of signal_a and signal_b at all times.

Knowing expressions update automatically models combinational logic in hardware.

4

Intermediate

Concurrent assignments vs. processes

🤔Before reading on: do you think concurrent assignments can include multiple statements like processes? Commit to your answer.

Concept: Concurrent assignments are single statements running in parallel, unlike processes which can have multiple sequential statements.

Concurrent assignments are simple and always active. Processes group multiple statements and run sequentially when triggered. Concurrent assignments are best for simple logic, while processes handle complex behavior.

Result

You understand when to use concurrent assignments or processes for hardware description.

Knowing the difference prevents mixing styles that cause confusion or errors.

5

Intermediate

Signal assignment delay and simulation

🤔Before reading on: do you think signal assignments update immediately or after a delay? Commit to your answer.

Concept: Signal assignments in VHDL happen after a small delay to simulate real hardware timing.

When you assign a signal, the new value doesn't appear instantly but after a delta delay. This models how signals propagate in circuits. For example: signal_a <= '1'; signal_b <= signal_a; signal_b changes after signal_a's update delay.

Result

Simulation reflects real hardware timing, avoiding unrealistic instant changes.

Understanding delays helps you write accurate hardware models and debug timing issues.

6

Advanced

Multiple concurrent assignments to one signal

🤔Before reading on: do you think assigning a signal multiple times concurrently is allowed? Commit to your answer.

Concept: Assigning a signal from multiple concurrent statements requires special handling like resolved signals.

If two concurrent assignments drive the same signal, VHDL uses resolution functions to combine values. For example, 'std_logic' signals use wired logic resolution to handle multiple drivers. Without this, the design is illegal or causes conflicts.

Result

You can model wired connections like buses or tri-state lines safely.

Knowing how multiple drivers work prevents design errors and models real hardware wiring.

7

Expert

Concurrent assignment in synthesis and optimization

🤔Before reading on: do you think all concurrent assignments map directly to hardware gates? Commit to your answer.

Concept: Synthesis tools translate concurrent assignments into hardware gates and optimize them for performance and area.

Concurrent assignments describe hardware behavior, but synthesis tools analyze and optimize them. For example, redundant logic may be removed, or signals combined. Understanding this helps write efficient code that synthesizes well.

Result

Your VHDL code becomes efficient hardware after synthesis.

Knowing synthesis behavior guides writing clean, optimized concurrent assignments.

Under the Hood

Concurrent signal assignments are evaluated continuously by the VHDL simulator or synthesis tool. Each assignment monitors its input signals and updates the target signal after a small delta delay. Internally, this models hardware gates and wires that operate in parallel, reflecting real circuit behavior. The simulator schedules updates in an event queue to maintain timing accuracy.

Why designed this way?

VHDL was designed to model hardware accurately, where many signals change simultaneously. Sequential programming languages can't express this parallelism naturally. Concurrent assignments allow describing hardware as it truly works, enabling simulation and synthesis to produce real circuits. Alternatives like purely sequential code would fail to capture hardware concurrency.

┌───────────────┐       ┌───────────────┐
│ Signal Inputs │──────▶│ Concurrent    │
│ (signal_a,b)  │       │ Assignments   │
└───────────────┘       └───────────────┘
         │                        │
         ▼                        ▼
   ┌───────────┐           ┌─────────────┐
   │ Event     │◀──────────│ Signal      │
   │ Scheduler │           │ Updates     │
   └───────────┘           └─────────────┘

Myth Busters - 4 Common Misconceptions

Quick: Do concurrent assignments execute one after another or all at once? Commit to your answer.

Common Belief: Concurrent assignments run one after another in order like program lines.

Reality: Concurrent assignments run in parallel, all active at the same time.

Why it matters: Thinking they run sequentially leads to wrong assumptions about signal timing and hardware behavior.

Quick: Can you assign a signal multiple times concurrently without issues? Commit to your answer.

Common Belief: You can assign the same signal multiple times concurrently without special rules.

Reality: Multiple concurrent drivers require resolved signal types or cause conflicts.

Why it matters: Ignoring this causes simulation errors or hardware conflicts in real circuits.

Quick: Do signal assignments update instantly or after a delay? Commit to your answer.

Common Belief: Signal assignments update instantly as soon as the code runs.

Reality: Signal assignments update after a delta delay to simulate real hardware timing.

Why it matters: Assuming instant updates causes misunderstanding of timing and race conditions.

Quick: Does concurrent assignment only work for simple signals? Commit to your answer.

Common Belief: Concurrent assignments can't handle complex expressions or types.

Reality: Concurrent assignments can use complex expressions and types, modeling rich hardware logic.

Why it matters: Underestimating this limits design expressiveness and leads to unnecessary process use.

Expert Zone

1

Concurrent assignments can be combined with 'when-else' and 'with-select' constructs for conditional hardware description, enabling compact and readable code.

2

The delta delay in signal updates is a simulation artifact; real hardware has physical delays, but delta delay helps order events logically.

3

Synthesis tools may optimize away some concurrent assignments if they detect constant or redundant logic, affecting debugging if not expected.

When NOT to use

Concurrent signal assignment is not suitable for describing sequential or stateful behavior that depends on clock edges or ordered steps. For such cases, use processes with sequential statements. Also, complex algorithms or state machines require processes rather than concurrent assignments.

Production Patterns

In real hardware designs, concurrent assignments are widely used for combinational logic like gates, multiplexers, and simple data routing. Designers combine them with processes for clocked logic. Conditional concurrent assignments using 'when-else' and 'with-select' are common for clean, readable hardware descriptions.

Connections

Parallel computing

Both involve multiple operations happening simultaneously.

Understanding concurrency in hardware helps grasp parallelism in software, where tasks run at the same time to improve speed.

Electrical circuits

Concurrent signal assignment models how electrical signals flow and change in real circuits.

Knowing basic electronics clarifies why signals update in parallel and why delays matter.

Event-driven simulation

Concurrent assignments rely on event-driven simulation to update signals after changes.

Understanding event queues and scheduling deepens comprehension of how VHDL simulates hardware timing.

Common Pitfalls

#1 Assigning a signal multiple times concurrently without using resolved types.

Wrong approach:

signal_a <= '1';
signal_a <= '0';

Correct approach:

Use resolved signal types like std_logic and proper driver logic:
signal_a : std_logic;
signal_a <= '1' when condition else '0';

Root cause:

Misunderstanding that signals can have only one driver unless resolved types handle multiple drivers.

#2 Using concurrent assignment inside a process block.

Wrong approach:

process(clk) begin
signal_a <= '1'; -- concurrent assignment inside process
end process;

Correct approach:

Use sequential assignment inside process:
process(clk) begin
if rising_edge(clk) then
signal_a <= '1';
end if;
end process;

Root cause:

Confusing concurrent assignment syntax with sequential assignment inside processes.

#3 Expecting signal updates to happen immediately after assignment.

Wrong approach:

signal_a <= '1';
if signal_a = '1' then
-- assume true immediately
end if;

Correct approach:

Understand signal updates occur after delta delay; use variables or wait statements for immediate effects inside processes.

Root cause:

Not knowing the delta delay semantics of signal assignments in VHDL.

Key Takeaways

Concurrent signal assignment models hardware signals changing simultaneously, reflecting real circuit behavior.

Assignments happen continuously and in parallel, not step-by-step like software code.

Signal updates occur after a small delay to simulate hardware timing accurately.

Multiple drivers on a signal require resolved types to avoid conflicts.

Concurrent assignments are ideal for combinational logic, while processes handle sequential behavior.

Practice

1. What does a concurrent signal assignment in VHDL do?
signal_name <= expression;

easy

A. Continuously updates the signal with the expression value in parallel

B. Executes the assignment only once at the start

C. Assigns the signal value sequentially after a delay

D. Creates a variable instead of a signal

Solution

1. Step 1: Understand concurrent assignment meaning

   Concurrent signal assignment updates the signal continuously and in parallel with other concurrent statements.

2. Step 2: Compare with other options

   Options B and C describe sequential or one-time behavior, which is incorrect. Creates a variable instead of a signal confuses signals with variables.

3. Final Answer:

   Continuously updates the signal with the expression value in parallel -> Option A

4. Quick Check:

   Concurrent assignment = continuous parallel update [OK]

Hint: Concurrent means always active and parallel [OK]

Common Mistakes:

• Thinking assignment happens only once
• Confusing signals with variables
• Assuming sequential execution

2. Which of the following is the correct syntax for a concurrent signal assignment in VHDL?

easy

A. signal_name <= expression;

B. signal_name = expression;

C. signal_name := expression;

D. signal_name -> expression;

Solution

1. Step 1: Recall VHDL signal assignment syntax

   In VHDL, concurrent signal assignment uses the "<=" operator.

2. Step 2: Eliminate incorrect options

   signal_name := expression; uses ":=", which is for variables, not signals. signal_name = expression; uses "=", which is not valid for signal assignment. signal_name -> expression; uses "->", which is invalid syntax.

3. Final Answer:

   signal_name <= expression; -> Option A

4. Quick Check:

   Signal assignment operator = <= [OK]

Hint: Use <= for signals, := for variables [OK]

Common Mistakes:

• Using := instead of <=
• Using = for signal assignment
• Confusing signal and variable syntax

3. Given the following VHDL code snippet:

signal a, b, c : std_logic;
b <= '1';
c <= b;
a <= c;

What is the value of signal a after simulation stabilizes?

medium

A. '0'

B. '1'

C. 'U' (uninitialized)

D. Simulation error

Solution

1. Step 1: Trace signal assignments

   b is assigned '1' concurrently, so b = '1'. Then c <= b means c = '1'. Then a <= c means a = '1'.

2. Step 2: Understand concurrent updates

   All assignments happen in parallel, so signals propagate the value '1' through b, c, and a.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   Signal chain propagates '1' [OK]

Hint: Follow signal chain step-by-step [OK]

Common Mistakes:

• Assuming initial 'U' remains
• Thinking assignments happen sequentially
• Confusing signal and variable updates

4. Identify the error in this VHDL concurrent signal assignment:

signal x : std_logic;
x = '1';

medium

A. Signal x must be declared as variable

B. Missing semicolon after signal declaration

C. Using '=' instead of '<=' for signal assignment

D. Signal cannot be assigned a constant

Solution

1. Step 1: Check assignment operator

   In VHDL, signals use '<=' for assignment, not '='.

2. Step 2: Verify other syntax

   Semicolon is present after declaration. Signal can be assigned constants. No need to declare as variable.

3. Final Answer:

   Using '=' instead of '<=' for signal assignment -> Option C

4. Quick Check:

   Signal assignment uses <= [OK]

Hint: Signals use <=, variables use := [OK]

Common Mistakes:

• Using = instead of <=
• Confusing signals with variables
• Thinking signals can't hold constants

5. You want to create a 2-bit signal out_sig that is always the bitwise AND of two 2-bit input signals in1 and in2. Which concurrent signal assignment correctly implements this?

hard

A. out_sig <= in1 & in2;

B. out_sig <= in1 or in2;

C. out_sig := in1 and in2;

D. out_sig <= in1 and in2;

Solution

1. Step 1: Identify correct operator for bitwise AND

   In VHDL, 'and' is the bitwise AND operator for std_logic_vector signals.

2. Step 2: Check syntax and operators

   out_sig <= in1 and in2; uses 'and' with '<=' which is correct. out_sig <= in1 & in2; uses '&' which is concatenation, not AND. out_sig := in1 and in2; uses ':=' which is for variables, not signals. out_sig <= in1 or in2; uses 'or' which is incorrect logic.

3. Final Answer:

   out_sig <= in1 and in2; -> Option D

4. Quick Check:

   Bitwise AND uses 'and' with <= [OK]

Hint: Use 'and' for bitwise AND, not '&' [OK]

Common Mistakes:

• Using '&' instead of 'and' for bitwise AND
• Using := instead of <=
• Using wrong logic operator