Concurrent signal assignment in VHDL - Time & Space Complexity

Time Complexity: Concurrent signal assignment

O(n)

Understanding Time Complexity

We want to understand how the time to update signals grows when using concurrent signal assignments in VHDL.

How does the number of signals affect the time it takes to update them all?

Scenario Under Consideration

Analyze the time complexity of the following code snippet.

architecture Behavioral of example is
  signal a, b, c, d : std_logic;
begin
  a <= b and c;
  b <= c or d;
  c <= d xor a;
  d <= a nand b;
end Behavioral;

This code assigns values to signals concurrently, each depending on other signals.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: Each concurrent assignment updates one signal based on others.
• How many times: All assignments happen simultaneously once per simulation cycle.

How Execution Grows With Input

As the number of concurrent assignments increases, the total updates grow linearly.

Input Size (n)	Approx. Operations
10	10 signal updates
100	100 signal updates
1000	1000 signal updates

Pattern observation: Doubling the number of signals doubles the work needed to update them.

Final Time Complexity

Time Complexity: O(n)

This means the time to update signals grows directly with the number of concurrent assignments.

Common Mistake

[X] Wrong: "Concurrent assignments happen all at once with zero time cost regardless of number."

[OK] Correct: Even though assignments are concurrent, each signal update takes time, so more signals mean more total work.

Interview Connect

Understanding how concurrent assignments scale helps you reason about hardware simulation speed and design efficiency.

Self-Check

"What if we changed concurrent assignments to sequential assignments inside a process? How would the time complexity change?"