Concurrent signal assignment in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of concurrent signal assignment with multiple drivers

What is the value of signal out_signal after simulation if the following concurrent assignments are used?

signal out_signal : std_logic;

begin
  out_signal <= '0';
  out_signal <= '1';
end;

VHDL

signal out_signal : std_logic;
begin
  out_signal <= '0';
  out_signal <= '1';
end;

A '0'

B X (unknown)

C Z (high impedance)

D '1'

💡 Hint

In VHDL, multiple concurrent assignments to the same std_logic signal create multiple drivers. Conflicting values ('0' and '1') resolve to 'X'.

In VHDL, concurrent signal assignments create separate drivers for the signal. std_logic is resolved, so the value is determined by the resolution function. '0' and '1' from different drivers conflict, resulting in 'X'.

❓ Predict Output

intermediate

Concurrent assignment with conditional signal assignment

Given the following concurrent signal assignment, what is the value of out_signal when enable = '0'?

signal out_signal : std_logic;
signal enable : std_logic;

begin
  out_signal <= '1' when enable = '1' else '0';
end;

VHDL

signal out_signal : std_logic;
signal enable : std_logic;
begin
  out_signal <= '1' when enable = '1' else '0';
end;

A '1'

B Z (high impedance)

C '0'

D X (unknown)

💡 Hint

Check the condition in the conditional assignment carefully.

The conditional assignment sets out_signal to '1' only if enable is '1'. Otherwise, it sets it to '0'. Since enable is '0', out_signal is '0'.

🔧 Debug

advanced

Identify the error in concurrent signal assignment

What error will the following VHDL code produce?

signal a, b : std_logic;
signal c : std_logic;

begin
  c <= a and b;
  c <= a or b;
end;

VHDL

signal a, b : std_logic;
signal c : std_logic;
begin
  c <= a and b;
  c <= a or b;
end;

A No error, c will be resolved from both assignments

B Multiple drivers error (signal driven by multiple sources without resolution)

C Syntax error: missing semicolon

D Type mismatch error

💡 Hint

std_logic is a resolved type, so multiple drivers from concurrent assignments are allowed.

In VHDL, signals of resolved types like std_logic can have multiple drivers from concurrent assignments. No error occurs; the value is the result of applying the resolution function to all driver values.

📝 Syntax

advanced

Correct syntax for concurrent signal assignment with selected signal assignment

Which of the following is the correct syntax for a concurrent selected signal assignment in VHDL?

A with sel select out_signal <= '0' when "00"; '1' when "01"; 'Z' when others;

B with sel select out_signal <= '0' when "00" else '1' when "01" else 'Z' when others;

C with sel select out_signal <= '0' when "00" | '1' when "01" | 'Z' when others;

D with sel select out_signal <= '0' when "00", '1' when "01", 'Z' when others;

💡 Hint

Remember the syntax uses commas to separate choices, not else or semicolons.

The correct syntax for selected signal assignment uses commas to separate choices and the keyword when for each choice, ending with a semicolon.

🚀 Application

expert

Number of drivers in concurrent signal assignment

Consider the following VHDL code snippet:

signal x, y, z : std_logic;
signal out_signal : std_logic;

begin
  out_signal <= x and y;
  out_signal <= z;
end;

How many drivers does out_signal have during simulation?

VHDL

signal x, y, z : std_logic;
signal out_signal : std_logic;
begin
  out_signal <= x and y;
  out_signal <= z;
end;

A 2 drivers

B 1 driver

C 3 drivers

D 0 drivers

💡 Hint

Each concurrent assignment to the same signal creates a driver.

Each concurrent assignment statement creates a separate driver for the signal. Here, out_signal has two concurrent assignments, so it has two drivers.

Practice

1. What does a concurrent signal assignment in VHDL do?
signal_name <= expression;

easy

A. Continuously updates the signal with the expression value in parallel

B. Executes the assignment only once at the start

C. Assigns the signal value sequentially after a delay

D. Creates a variable instead of a signal

Solution

1. Step 1: Understand concurrent assignment meaning

   Concurrent signal assignment updates the signal continuously and in parallel with other concurrent statements.

2. Step 2: Compare with other options

   Options B and C describe sequential or one-time behavior, which is incorrect. Creates a variable instead of a signal confuses signals with variables.

3. Final Answer:

   Continuously updates the signal with the expression value in parallel -> Option A

4. Quick Check:

   Concurrent assignment = continuous parallel update [OK]

Hint: Concurrent means always active and parallel [OK]

Common Mistakes:

• Thinking assignment happens only once
• Confusing signals with variables
• Assuming sequential execution

2. Which of the following is the correct syntax for a concurrent signal assignment in VHDL?

easy

A. signal_name <= expression;

B. signal_name = expression;

C. signal_name := expression;

D. signal_name -> expression;

Solution

1. Step 1: Recall VHDL signal assignment syntax

   In VHDL, concurrent signal assignment uses the "<=" operator.

2. Step 2: Eliminate incorrect options

   signal_name := expression; uses ":=", which is for variables, not signals. signal_name = expression; uses "=", which is not valid for signal assignment. signal_name -> expression; uses "->", which is invalid syntax.

3. Final Answer:

   signal_name <= expression; -> Option A

4. Quick Check:

   Signal assignment operator = <= [OK]

Hint: Use <= for signals, := for variables [OK]

Common Mistakes:

• Using := instead of <=
• Using = for signal assignment
• Confusing signal and variable syntax

3. Given the following VHDL code snippet:

signal a, b, c : std_logic;
b <= '1';
c <= b;
a <= c;

What is the value of signal a after simulation stabilizes?

medium

A. '0'

B. '1'

C. 'U' (uninitialized)

D. Simulation error

Solution

1. Step 1: Trace signal assignments

   b is assigned '1' concurrently, so b = '1'. Then c <= b means c = '1'. Then a <= c means a = '1'.

2. Step 2: Understand concurrent updates

   All assignments happen in parallel, so signals propagate the value '1' through b, c, and a.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   Signal chain propagates '1' [OK]

Hint: Follow signal chain step-by-step [OK]

Common Mistakes:

• Assuming initial 'U' remains
• Thinking assignments happen sequentially
• Confusing signal and variable updates

4. Identify the error in this VHDL concurrent signal assignment:

signal x : std_logic;
x = '1';

medium

A. Signal x must be declared as variable

B. Missing semicolon after signal declaration

C. Using '=' instead of '<=' for signal assignment

D. Signal cannot be assigned a constant

Solution

1. Step 1: Check assignment operator

   In VHDL, signals use '<=' for assignment, not '='.

2. Step 2: Verify other syntax

   Semicolon is present after declaration. Signal can be assigned constants. No need to declare as variable.

3. Final Answer:

   Using '=' instead of '<=' for signal assignment -> Option C

4. Quick Check:

   Signal assignment uses <= [OK]

Hint: Signals use <=, variables use := [OK]

Common Mistakes:

• Using = instead of <=
• Confusing signals with variables
• Thinking signals can't hold constants

5. You want to create a 2-bit signal out_sig that is always the bitwise AND of two 2-bit input signals in1 and in2. Which concurrent signal assignment correctly implements this?

hard

A. out_sig <= in1 & in2;

B. out_sig <= in1 or in2;

C. out_sig := in1 and in2;

D. out_sig <= in1 and in2;

Solution

1. Step 1: Identify correct operator for bitwise AND

   In VHDL, 'and' is the bitwise AND operator for std_logic_vector signals.

2. Step 2: Check syntax and operators

   out_sig <= in1 and in2; uses 'and' with '<=' which is correct. out_sig <= in1 & in2; uses '&' which is concatenation, not AND. out_sig := in1 and in2; uses ':=' which is for variables, not signals. out_sig <= in1 or in2; uses 'or' which is incorrect logic.

3. Final Answer:

   out_sig <= in1 and in2; -> Option D

4. Quick Check:

   Bitwise AND uses 'and' with <= [OK]

Hint: Use 'and' for bitwise AND, not '&' [OK]

Common Mistakes:

• Using '&' instead of 'and' for bitwise AND
• Using := instead of <=
• Using wrong logic operator