Concurrent signal assignment in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of concurrent signal assignment with multiple drivers

What is the value of signal out_signal after simulation if the following concurrent assignments are used?

signal out_signal : std_logic;

begin
  out_signal <= '0';
  out_signal <= '1';
end;

VHDL

signal out_signal : std_logic;
begin
  out_signal <= '0';
  out_signal <= '1';
end;

A '0'

B X (unknown)

C Z (high impedance)

D '1'

💡 Hint

In VHDL, multiple concurrent assignments to the same std_logic signal create multiple drivers. Conflicting values ('0' and '1') resolve to 'X'.

In VHDL, concurrent signal assignments create separate drivers for the signal. std_logic is resolved, so the value is determined by the resolution function. '0' and '1' from different drivers conflict, resulting in 'X'.

❓ Predict Output

intermediate

Concurrent assignment with conditional signal assignment

Given the following concurrent signal assignment, what is the value of out_signal when enable = '0'?

signal out_signal : std_logic;
signal enable : std_logic;

begin
  out_signal <= '1' when enable = '1' else '0';
end;

VHDL

signal out_signal : std_logic;
signal enable : std_logic;
begin
  out_signal <= '1' when enable = '1' else '0';
end;

A '1'

B Z (high impedance)

C '0'

D X (unknown)

💡 Hint

Check the condition in the conditional assignment carefully.

The conditional assignment sets out_signal to '1' only if enable is '1'. Otherwise, it sets it to '0'. Since enable is '0', out_signal is '0'.

🔧 Debug

advanced

Identify the error in concurrent signal assignment

What error will the following VHDL code produce?

signal a, b : std_logic;
signal c : std_logic;

begin
  c <= a and b;
  c <= a or b;
end;

VHDL

signal a, b : std_logic;
signal c : std_logic;
begin
  c <= a and b;
  c <= a or b;
end;

A No error, c will be resolved from both assignments

B Multiple drivers error (signal driven by multiple sources without resolution)

C Syntax error: missing semicolon

D Type mismatch error

💡 Hint

std_logic is a resolved type, so multiple drivers from concurrent assignments are allowed.

In VHDL, signals of resolved types like std_logic can have multiple drivers from concurrent assignments. No error occurs; the value is the result of applying the resolution function to all driver values.

📝 Syntax

advanced

Correct syntax for concurrent signal assignment with selected signal assignment

Which of the following is the correct syntax for a concurrent selected signal assignment in VHDL?

A with sel select out_signal <= '0' when "00"; '1' when "01"; 'Z' when others;

B with sel select out_signal <= '0' when "00" else '1' when "01" else 'Z' when others;

C with sel select out_signal <= '0' when "00" | '1' when "01" | 'Z' when others;

D with sel select out_signal <= '0' when "00", '1' when "01", 'Z' when others;

💡 Hint

Remember the syntax uses commas to separate choices, not else or semicolons.

The correct syntax for selected signal assignment uses commas to separate choices and the keyword when for each choice, ending with a semicolon.

🚀 Application

expert

Number of drivers in concurrent signal assignment

Consider the following VHDL code snippet:

signal x, y, z : std_logic;
signal out_signal : std_logic;

begin
  out_signal <= x and y;
  out_signal <= z;
end;

How many drivers does out_signal have during simulation?

VHDL

signal x, y, z : std_logic;
signal out_signal : std_logic;
begin
  out_signal <= x and y;
  out_signal <= z;
end;

A 2 drivers

B 1 driver

C 3 drivers

D 0 drivers

💡 Hint

Each concurrent assignment to the same signal creates a driver.

Each concurrent assignment statement creates a separate driver for the signal. Here, out_signal has two concurrent assignments, so it has two drivers.