Concurrent signal assignment in VHDL - Mini Project: Build & Apply

Concurrent Signal Assignment in VHDL

📖 Scenario: You are designing a simple digital circuit that controls two LEDs based on two input switches. You want to assign the LED signals concurrently so that they update immediately when the switches change.

🎯 Goal: Build a VHDL design that uses concurrent signal assignment statements to control two LEDs from two switches.

📋 What You'll Learn

Create signals for two switches and two LEDs

Assign LED signals concurrently based on switch signals

Use simple concurrent signal assignment statements

Print the final LED signal values in simulation

💡 Why This Matters

🌍 Real World

Concurrent signal assignment is used in digital hardware design to update outputs immediately based on inputs, such as controlling LEDs, motors, or other devices.

💼 Career

Understanding concurrent signal assignment is essential for FPGA and ASIC designers who write VHDL code to implement hardware logic.

1

Create input and output signals

Create two signals called switch1 and switch2 of type std_logic and initialize both to '0'. Also create two signals called led1 and led2 of type std_logic.

VHDL

-- Declare signals for switches and LEDs
-- Your code here

Hint

Signals are declared with the keyword signal. Initialize switch1 and switch2 to '0'.

2

Set switch1 to '1' to simulate pressing the switch

Assign the value '1' to the signal switch1 to simulate pressing the first switch.

VHDL

signal switch1 : std_logic := '0';
signal switch2 : std_logic := '0';
signal led1 : std_logic;
signal led2 : std_logic;

-- Set switch1 to '1'
-- Your code here

Hint

Change the initialization of switch1 to '1'.

3

Assign LEDs concurrently based on switches

Use concurrent signal assignment statements to assign led1 the value of switch1 and led2 the value of switch2.

VHDL

signal switch1 : std_logic := '1';
signal switch2 : std_logic := '0';
signal led1 : std_logic;
signal led2 : std_logic;

-- Assign led1 and led2 concurrently
-- Your code here

Hint

Use the <= operator for concurrent signal assignment outside processes.

4

Print the LED values in simulation

Write a process that prints the values of led1 and led2 using report statements to show the LED states.

VHDL

signal switch1 : std_logic := '1';
signal switch2 : std_logic := '0';
signal led1 : std_logic;
signal led2 : std_logic;

led1 <= switch1;
led2 <= switch2;

-- Add a process to print LED values
-- Your code here

Hint

Use a process with a wait statement and a report to display signal values in simulation.

Practice

1. What does a concurrent signal assignment in VHDL do?
signal_name <= expression;

easy

A. Continuously updates the signal with the expression value in parallel

B. Executes the assignment only once at the start

C. Assigns the signal value sequentially after a delay

D. Creates a variable instead of a signal

Solution

1. Step 1: Understand concurrent assignment meaning

   Concurrent signal assignment updates the signal continuously and in parallel with other concurrent statements.

2. Step 2: Compare with other options

   Options B and C describe sequential or one-time behavior, which is incorrect. Creates a variable instead of a signal confuses signals with variables.

3. Final Answer:

   Continuously updates the signal with the expression value in parallel -> Option A

4. Quick Check:

   Concurrent assignment = continuous parallel update [OK]

Hint: Concurrent means always active and parallel [OK]

Common Mistakes:

• Thinking assignment happens only once
• Confusing signals with variables
• Assuming sequential execution

2. Which of the following is the correct syntax for a concurrent signal assignment in VHDL?

easy

A. signal_name <= expression;

B. signal_name = expression;

C. signal_name := expression;

D. signal_name -> expression;

Solution

1. Step 1: Recall VHDL signal assignment syntax

   In VHDL, concurrent signal assignment uses the "<=" operator.

2. Step 2: Eliminate incorrect options

   signal_name := expression; uses ":=", which is for variables, not signals. signal_name = expression; uses "=", which is not valid for signal assignment. signal_name -> expression; uses "->", which is invalid syntax.

3. Final Answer:

   signal_name <= expression; -> Option A

4. Quick Check:

   Signal assignment operator = <= [OK]

Hint: Use <= for signals, := for variables [OK]

Common Mistakes:

• Using := instead of <=
• Using = for signal assignment
• Confusing signal and variable syntax

3. Given the following VHDL code snippet:

signal a, b, c : std_logic;
b <= '1';
c <= b;
a <= c;

What is the value of signal a after simulation stabilizes?

medium

A. '0'

B. '1'

C. 'U' (uninitialized)

D. Simulation error

Solution

1. Step 1: Trace signal assignments

   b is assigned '1' concurrently, so b = '1'. Then c <= b means c = '1'. Then a <= c means a = '1'.

2. Step 2: Understand concurrent updates

   All assignments happen in parallel, so signals propagate the value '1' through b, c, and a.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   Signal chain propagates '1' [OK]

Hint: Follow signal chain step-by-step [OK]

Common Mistakes:

• Assuming initial 'U' remains
• Thinking assignments happen sequentially
• Confusing signal and variable updates

4. Identify the error in this VHDL concurrent signal assignment:

signal x : std_logic;
x = '1';

medium

A. Signal x must be declared as variable

B. Missing semicolon after signal declaration

C. Using '=' instead of '<=' for signal assignment

D. Signal cannot be assigned a constant

Solution

1. Step 1: Check assignment operator

   In VHDL, signals use '<=' for assignment, not '='.

2. Step 2: Verify other syntax

   Semicolon is present after declaration. Signal can be assigned constants. No need to declare as variable.

3. Final Answer:

   Using '=' instead of '<=' for signal assignment -> Option C

4. Quick Check:

   Signal assignment uses <= [OK]

Hint: Signals use <=, variables use := [OK]

Common Mistakes:

• Using = instead of <=
• Confusing signals with variables
• Thinking signals can't hold constants

5. You want to create a 2-bit signal out_sig that is always the bitwise AND of two 2-bit input signals in1 and in2. Which concurrent signal assignment correctly implements this?

hard

A. out_sig <= in1 & in2;

B. out_sig <= in1 or in2;

C. out_sig := in1 and in2;

D. out_sig <= in1 and in2;

Solution

1. Step 1: Identify correct operator for bitwise AND

   In VHDL, 'and' is the bitwise AND operator for std_logic_vector signals.

2. Step 2: Check syntax and operators

   out_sig <= in1 and in2; uses 'and' with '<=' which is correct. out_sig <= in1 & in2; uses '&' which is concatenation, not AND. out_sig := in1 and in2; uses ':=' which is for variables, not signals. out_sig <= in1 or in2; uses 'or' which is incorrect logic.

3. Final Answer:

   out_sig <= in1 and in2; -> Option D

4. Quick Check:

   Bitwise AND uses 'and' with <= [OK]

Hint: Use 'and' for bitwise AND, not '&' [OK]

Common Mistakes:

• Using '&' instead of 'and' for bitwise AND
• Using := instead of <=
• Using wrong logic operator