Why memory blocks are needed in Verilog - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a memory block of 8 bits wide and 16 words deep.

Verilog

reg [7:0] memory [0:[1]];

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A8

B16

C15

D7

Attempts:

3 left

💡 Hint

Common Mistakes

Using 16 as the highest index instead of 15.

The memory block has 16 words, indexed from 0 to 15, so the highest index is 15.

2fill in blank

medium

Complete the code to read data from memory at address 'addr'.

Verilog

assign data_out = memory[[1]];

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Adata_in

Bclk

Cdata_out

Daddr

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_in or clk instead of the address.

The address 'addr' is used to index the memory to read the data.

3fill in blank

hard

Fix the error in the code to write data to memory on the rising edge of clock.

Verilog

always @(posedge clk) begin
  if (write_enable) memory[[1]] <= data_in;
end

Drag options to blanks, or click blank then click option'

Aaddr

Bdata_out

Cclk

Dwrite_enable

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_out or clk as the index.

The address 'addr' is needed to specify where to write the data in memory.

4fill in blank

hard

Fill both blanks to create a memory block and initialize it with zeros.

Verilog

reg [7:0] memory [0:[1]];
initial begin
  integer i;
  for (i = 0; i [2] 16; i = i + 1) memory[i] = 8'b0;
end

Drag options to blanks, or click blank then click option'

A15

B16

C<=

D<

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'i <= 16' instead of 'i < 16' in the loop condition.

The memory has 16 words indexed 0 to 15, and the loop runs while i is less than 16 (i < 16), so the last index is 15.

5fill in blank

hard

Fill all three blanks to implement a synchronous read and write memory block.

Verilog

reg [7:0] memory [0:[1]];
always @(posedge clk) begin
  if (write_enable) memory[[2]] <= data_in;
  data_out <= memory[[3]];
end

Drag options to blanks, or click blank then click option'

A7

Baddr

Cread_addr

D15

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong indices or same address for read and write.

The memory has 16 words indexed 0 to 15. 'addr' is used for writing, and 'read_addr' is used for reading.