Simulation time control in VHDL - Step-by-Step Execution

Concept Flow - Simulation time control

Start Simulation

↓

Wait for time delay

↓

Update signals

↓

Check next wait or end

Yes No↓

Continue

Simulation time control in VHDL uses wait statements to pause simulation, update signals, and proceed step-by-step until the simulation ends.

Execution Sample

VHDL

process
begin
  a <= '0';
  wait for 10 ns;
  a <= '1';
  wait for 20 ns;
  wait;
end process;

This code sets signal 'a' to '0', waits 10 ns, sets 'a' to '1', waits 20 ns, then stops simulation.

Execution Table

Step	Simulation Time (ns)	Signal 'a'	Action	Next Action
1	0	'0'	Assign '0' to a	wait for 10 ns
2	10	'0'	Waited 10 ns	Assign '1' to a
3	10	'1'	Assign '1' to a	wait for 20 ns
4	30	'1'	Waited 20 ns	wait (infinite)
5	30	'1'	Simulation stops (wait)	End

💡 Simulation stops at infinite wait statement after 30 ns

Variable Tracker

Variable	Initial	After Step 2 (10 ns)	After Step 4 (30 ns)	Final
a	U (undefined)	'0'	'1'	'1'

Key Moments - 3 Insights

Why does the simulation stop after the last wait statement?

The last 'wait;' statement causes the simulation to pause indefinitely, stopping further execution as shown in step 5 of the execution_table.

Does the signal 'a' change during the wait periods?

No, signal 'a' keeps its last assigned value during wait periods, as seen between steps 2 and 4 in the execution_table.

What happens if we remove the final 'wait;' statement?

Without the final 'wait;', the process would restart or end immediately depending on context, but here it stops because the infinite wait halts simulation (step 5).

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of signal 'a' at simulation time 10 ns?

A '0'

B '1'

C U (undefined)

D X (unknown)

💡 Hint

Check row 2 in execution_table where simulation time is 10 ns.

At which step does the simulation time reach 30 ns?

A Step 2

B Step 4

C Step 3

D Step 5

💡 Hint

Look at the 'Simulation Time (ns)' column in execution_table rows.

If the final 'wait;' statement is removed, what happens to the simulation?

A Signal 'a' resets to '0'

B Simulation stops immediately after 30 ns

C Simulation continues or restarts the process

D Simulation time resets to 0 ns

💡 Hint

Refer to key_moments explanation about the effect of removing the final wait statement.

Concept Snapshot

VHDL simulation time control uses 'wait' statements to pause simulation.
Syntax: 'wait for <time>;' pauses for specified time.
Signals update immediately before wait.
'wait;' alone pauses indefinitely, stopping simulation.
Use waits to control timing and signal changes step-by-step.

Full Transcript

This example shows how VHDL simulation time control works using wait statements. The process starts by assigning '0' to signal 'a' at time 0 ns. Then it waits for 10 ns, keeping 'a' at '0'. After 10 ns, 'a' is assigned '1'. Next, it waits for 20 ns, holding 'a' at '1'. Finally, the process executes an infinite wait statement, which stops the simulation at 30 ns. The variable tracker shows 'a' changing from undefined to '0' and then to '1'. Key moments clarify why the simulation stops and how signals behave during waits. The quiz tests understanding of signal values at specific times and the effect of removing the final wait.