Simulation time control in VHDL - Step-by-Step Execution

Concept Flow - Simulation time control

Start Simulation

↓

Wait for time delay

↓

Update signals

↓

Check next wait or end

Yes No↓

Continue

Simulation time control in VHDL uses wait statements to pause simulation, update signals, and proceed step-by-step until the simulation ends.

Execution Sample

VHDL

process
begin
  a <= '0';
  wait for 10 ns;
  a <= '1';
  wait for 20 ns;
  wait;
end process;

This code sets signal 'a' to '0', waits 10 ns, sets 'a' to '1', waits 20 ns, then stops simulation.

Execution Table

Step	Simulation Time (ns)	Signal 'a'	Action	Next Action
1	0	'0'	Assign '0' to a	wait for 10 ns
2	10	'0'	Waited 10 ns	Assign '1' to a
3	10	'1'	Assign '1' to a	wait for 20 ns
4	30	'1'	Waited 20 ns	wait (infinite)
5	30	'1'	Simulation stops (wait)	End

💡 Simulation stops at infinite wait statement after 30 ns

Variable Tracker

Variable	Initial	After Step 2 (10 ns)	After Step 4 (30 ns)	Final
a	U (undefined)	'0'	'1'	'1'

Key Moments - 3 Insights

Why does the simulation stop after the last wait statement?

The last 'wait;' statement causes the simulation to pause indefinitely, stopping further execution as shown in step 5 of the execution_table.

Does the signal 'a' change during the wait periods?

No, signal 'a' keeps its last assigned value during wait periods, as seen between steps 2 and 4 in the execution_table.

What happens if we remove the final 'wait;' statement?

Without the final 'wait;', the process would restart or end immediately depending on context, but here it stops because the infinite wait halts simulation (step 5).

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of signal 'a' at simulation time 10 ns?

A '0'

B '1'

C U (undefined)

D X (unknown)

💡 Hint

Check row 2 in execution_table where simulation time is 10 ns.

At which step does the simulation time reach 30 ns?

A Step 2

B Step 4

C Step 3

D Step 5

💡 Hint

Look at the 'Simulation Time (ns)' column in execution_table rows.

If the final 'wait;' statement is removed, what happens to the simulation?

A Signal 'a' resets to '0'

B Simulation stops immediately after 30 ns

C Simulation continues or restarts the process

D Simulation time resets to 0 ns

💡 Hint

Refer to key_moments explanation about the effect of removing the final wait statement.

Concept Snapshot

VHDL simulation time control uses 'wait' statements to pause simulation.
Syntax: 'wait for <time>;' pauses for specified time.
Signals update immediately before wait.
'wait;' alone pauses indefinitely, stopping simulation.
Use waits to control timing and signal changes step-by-step.

Full Transcript

This example shows how VHDL simulation time control works using wait statements. The process starts by assigning '0' to signal 'a' at time 0 ns. Then it waits for 10 ns, keeping 'a' at '0'. After 10 ns, 'a' is assigned '1'. Next, it waits for 20 ns, holding 'a' at '1'. Finally, the process executes an infinite wait statement, which stops the simulation at 30 ns. The variable tracker shows 'a' changing from undefined to '0' and then to '1'. Key moments clarify why the simulation stops and how signals behave during waits. The quiz tests understanding of signal values at specific times and the effect of removing the final wait.

Practice

1. What does the VHDL statement wait for 10 ns; do in a testbench?

easy

A. Pauses the simulation for 10 nanoseconds before continuing.

B. Waits until a signal changes value.

C. Waits until a condition becomes true.

D. Ends the simulation immediately.

Solution

1. Step 1: Understand the wait for statement

   The wait for statement pauses the simulation for a fixed amount of time.

2. Step 2: Apply to the given time

   Here, it pauses for 10 nanoseconds before continuing the simulation.

3. Final Answer:

   Pauses the simulation for 10 nanoseconds before continuing. -> Option A

4. Quick Check:

   wait for 10 ns; = Pause 10 ns [OK]

Hint: Remember: 'wait for' pauses fixed time, not conditions. [OK]

Common Mistakes:

• Confusing 'wait for' with 'wait until' or 'wait on'.
• Thinking it waits for a signal change.
• Assuming it ends simulation.

2. Which of the following is the correct syntax to wait until signal clk becomes '1' in VHDL?

easy

A. wait for clk = '1';

B. wait on clk = '1';

C. wait until clk = '1';

D. wait clk = '1';

Solution

1. Step 1: Identify correct wait syntax for condition

   The correct syntax to wait for a condition is wait until condition;.

2. Step 2: Apply to signal clk equals '1'

   So, wait until clk = '1'; waits until clk becomes '1'.

3. Final Answer:

   wait until clk = '1'; -> Option C

4. Quick Check:

   Condition wait = wait until [OK]

Hint: Use 'wait until' for conditions, not 'wait for' or 'wait on'. [OK]

Common Mistakes:

• Using 'wait for' with a condition instead of time.
• Using 'wait on' incorrectly with a condition.
• Omitting 'until' keyword.

3. Consider the following VHDL testbench snippet:

signal clk : std_logic := '0';
begin
  clk_process: process
  begin
    clk <= '0';
    wait for 5 ns;
    clk <= '1';
    wait for 5 ns;
  end process;

What is the total time for one full clock cycle of clk?

medium

A. 5 ns

B. 15 ns

C. 20 ns

D. 10 ns

Solution

1. Step 1: Analyze the clock toggling times

   The clock is set to '0', then waits 5 ns, then set to '1', then waits 5 ns.

2. Step 2: Calculate total cycle time

   One full cycle is from '0' to '1' and back to '0', which takes 5 ns + 5 ns = 10 ns.

3. Final Answer:

   10 ns -> Option D

4. Quick Check:

   5 ns + 5 ns = 10 ns [OK]

Hint: Add all wait times between signal changes for full cycle. [OK]

Common Mistakes:

• Counting only one wait period.
• Confusing signal assignments with wait times.
• Ignoring that both waits add up.

4. Identify the error in this VHDL wait statement:

wait until clk = 1;

medium

A. Missing semicolon at the end.

B. Signal value should be in single quotes: '1'.

C. Cannot use 'wait until' with signals.

D. The statement should be 'wait for clk = 1;'.

Solution

1. Step 1: Check signal value syntax

   In VHDL, std_logic values must be in single quotes, e.g., '1', not 1.

2. Step 2: Confirm correct usage of 'wait until'

   The syntax wait until clk = '1'; is correct; only the quotes are missing.

3. Final Answer:

   Signal value should be in single quotes: '1'. -> Option B

4. Quick Check:

   std_logic values need single quotes [OK]

Hint: Use single quotes for std_logic values in conditions. [OK]

Common Mistakes:

• Using numeric 1 instead of character '1'.
• Confusing 'wait until' with 'wait for'.
• Omitting semicolon (though not the main error here).

5. You want to create a testbench process that waits for a signal ready to become '1', then waits an additional 20 ns before starting the next operation. Which sequence of wait statements correctly achieves this?

hard

A. wait until ready = '1'; wait for 20 ns;

B. wait for 20 ns; wait until ready = '1';

C. wait on ready; wait for 20 ns;

D. wait until ready = 1 and wait for 20 ns;

Solution

1. Step 1: Wait for the signal ready to become '1'

   The correct syntax is wait until ready = '1'; to pause until the signal is '1'.

2. Step 2: Wait an additional fixed time

   After the signal is '1', use wait for 20 ns; to delay 20 nanoseconds before continuing.

3. Final Answer:

   wait until ready = '1'; wait for 20 ns; -> Option A

4. Quick Check:

   Condition wait then fixed wait = wait until ready = '1'; wait for 20 ns; [OK]

Hint: Wait for condition first, then fixed delay. [OK]

Common Mistakes:

• Reversing the order of waits.
• Using 'wait on' without condition.
• Missing single quotes around '1'.