Simulation time control in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the purpose of wait for statement in VHDL simulation?

The wait for statement pauses the simulation for a specified amount of time, allowing you to control when events happen during simulation.

intermediate

How does wait until differ from wait for in VHDL?

wait until pauses simulation until a specific condition becomes true, while wait for pauses for a fixed time period regardless of conditions.

beginner

What does the after keyword do in signal assignments during simulation?

The after keyword schedules a signal to change its value after a specified delay, simulating real hardware timing.

intermediate

Explain the difference between wait on and wait until statements.

wait on pauses simulation until any signal in a list changes, while wait until pauses until a condition is true.

beginner

Why is controlling simulation time important in VHDL testbenches?

Controlling simulation time lets you test how your design behaves over time, check timing, and simulate real hardware delays accurately.

Which VHDL statement pauses simulation for a fixed time?

A wait for 10 ns;

B wait until clk = '1';

C wait on signal_a;

D signal <= '1' after 5 ns;

wait for pauses simulation for a fixed time period.

What does signal <= '0' after 20 ns; do?

A Immediately sets signal to '0'

B Sets signal to '0' after 20 ns delay

C Waits 20 ns then sets signal to '1'

D Pauses simulation for 20 ns

The signal changes to '0' after a 20 ns delay.

Which statement waits until a condition is true?

A wait until reset = '0';

B wait for 5 ns;

C wait on clk;

D signal <= '1' after 10 ns;

wait until pauses simulation until the condition is true.

What happens when you use wait on signal_a, signal_b;?

A Signals signal_a and signal_b are assigned new values

B Simulation pauses for a fixed time

C Simulation pauses until a condition is true

D Simulation pauses until either signal_a or signal_b changes

wait on waits for any listed signal to change.

Why use delays like after 10 ns in testbenches?

A To ignore timing issues

B To speed up simulation

C To simulate real hardware timing delays

D To reset signals immediately

Delays help simulate how hardware behaves over time.

Describe how you can pause a VHDL simulation for a specific time and then resume.

Think about how to tell the simulator to wait a certain number of nanoseconds.

Explain the difference between wait until and wait on statements in VHDL simulation.

One waits for a condition, the other waits for signal changes.