Simulation time control in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the purpose of wait for statement in VHDL simulation?

The wait for statement pauses the simulation for a specified amount of time, allowing you to control when events happen during simulation.

intermediate

How does wait until differ from wait for in VHDL?

wait until pauses simulation until a specific condition becomes true, while wait for pauses for a fixed time period regardless of conditions.

beginner

What does the after keyword do in signal assignments during simulation?

The after keyword schedules a signal to change its value after a specified delay, simulating real hardware timing.

intermediate

Explain the difference between wait on and wait until statements.

wait on pauses simulation until any signal in a list changes, while wait until pauses until a condition is true.

beginner

Why is controlling simulation time important in VHDL testbenches?

Controlling simulation time lets you test how your design behaves over time, check timing, and simulate real hardware delays accurately.

Which VHDL statement pauses simulation for a fixed time?

A wait for 10 ns;

B wait until clk = '1';

C wait on signal_a;

D signal <= '1' after 5 ns;

wait for pauses simulation for a fixed time period.

What does signal <= '0' after 20 ns; do?

A Immediately sets signal to '0'

B Sets signal to '0' after 20 ns delay

C Waits 20 ns then sets signal to '1'

D Pauses simulation for 20 ns

The signal changes to '0' after a 20 ns delay.

Which statement waits until a condition is true?

A wait until reset = '0';

B wait for 5 ns;

C wait on clk;

D signal <= '1' after 10 ns;

wait until pauses simulation until the condition is true.

What happens when you use wait on signal_a, signal_b;?

A Signals signal_a and signal_b are assigned new values

B Simulation pauses for a fixed time

C Simulation pauses until a condition is true

D Simulation pauses until either signal_a or signal_b changes

wait on waits for any listed signal to change.

Why use delays like after 10 ns in testbenches?

A To ignore timing issues

B To speed up simulation

C To simulate real hardware timing delays

D To reset signals immediately

Delays help simulate how hardware behaves over time.

Describe how you can pause a VHDL simulation for a specific time and then resume.

Think about how to tell the simulator to wait a certain number of nanoseconds.

Explain the difference between wait until and wait on statements in VHDL simulation.

One waits for a condition, the other waits for signal changes.

Practice

1. What does the VHDL statement wait for 10 ns; do in a testbench?

easy

A. Pauses the simulation for 10 nanoseconds before continuing.

B. Waits until a signal changes value.

C. Waits until a condition becomes true.

D. Ends the simulation immediately.

Solution

1. Step 1: Understand the wait for statement

   The wait for statement pauses the simulation for a fixed amount of time.

2. Step 2: Apply to the given time

   Here, it pauses for 10 nanoseconds before continuing the simulation.

3. Final Answer:

   Pauses the simulation for 10 nanoseconds before continuing. -> Option A

4. Quick Check:

   wait for 10 ns; = Pause 10 ns [OK]

Hint: Remember: 'wait for' pauses fixed time, not conditions. [OK]

Common Mistakes:

• Confusing 'wait for' with 'wait until' or 'wait on'.
• Thinking it waits for a signal change.
• Assuming it ends simulation.

2. Which of the following is the correct syntax to wait until signal clk becomes '1' in VHDL?

easy

A. wait for clk = '1';

B. wait on clk = '1';

C. wait until clk = '1';

D. wait clk = '1';

Solution

1. Step 1: Identify correct wait syntax for condition

   The correct syntax to wait for a condition is wait until condition;.

2. Step 2: Apply to signal clk equals '1'

   So, wait until clk = '1'; waits until clk becomes '1'.

3. Final Answer:

   wait until clk = '1'; -> Option C

4. Quick Check:

   Condition wait = wait until [OK]

Hint: Use 'wait until' for conditions, not 'wait for' or 'wait on'. [OK]

Common Mistakes:

• Using 'wait for' with a condition instead of time.
• Using 'wait on' incorrectly with a condition.
• Omitting 'until' keyword.

3. Consider the following VHDL testbench snippet:

signal clk : std_logic := '0';
begin
  clk_process: process
  begin
    clk <= '0';
    wait for 5 ns;
    clk <= '1';
    wait for 5 ns;
  end process;

What is the total time for one full clock cycle of clk?

medium

A. 5 ns

B. 15 ns

C. 20 ns

D. 10 ns

Solution

1. Step 1: Analyze the clock toggling times

   The clock is set to '0', then waits 5 ns, then set to '1', then waits 5 ns.

2. Step 2: Calculate total cycle time

   One full cycle is from '0' to '1' and back to '0', which takes 5 ns + 5 ns = 10 ns.

3. Final Answer:

   10 ns -> Option D

4. Quick Check:

   5 ns + 5 ns = 10 ns [OK]

Hint: Add all wait times between signal changes for full cycle. [OK]

Common Mistakes:

• Counting only one wait period.
• Confusing signal assignments with wait times.
• Ignoring that both waits add up.

4. Identify the error in this VHDL wait statement:

wait until clk = 1;

medium

A. Missing semicolon at the end.

B. Signal value should be in single quotes: '1'.

C. Cannot use 'wait until' with signals.

D. The statement should be 'wait for clk = 1;'.

Solution

1. Step 1: Check signal value syntax

   In VHDL, std_logic values must be in single quotes, e.g., '1', not 1.

2. Step 2: Confirm correct usage of 'wait until'

   The syntax wait until clk = '1'; is correct; only the quotes are missing.

3. Final Answer:

   Signal value should be in single quotes: '1'. -> Option B

4. Quick Check:

   std_logic values need single quotes [OK]

Hint: Use single quotes for std_logic values in conditions. [OK]

Common Mistakes:

• Using numeric 1 instead of character '1'.
• Confusing 'wait until' with 'wait for'.
• Omitting semicolon (though not the main error here).

5. You want to create a testbench process that waits for a signal ready to become '1', then waits an additional 20 ns before starting the next operation. Which sequence of wait statements correctly achieves this?

hard

A. wait until ready = '1'; wait for 20 ns;

B. wait for 20 ns; wait until ready = '1';

C. wait on ready; wait for 20 ns;

D. wait until ready = 1 and wait for 20 ns;

Solution

1. Step 1: Wait for the signal ready to become '1'

   The correct syntax is wait until ready = '1'; to pause until the signal is '1'.

2. Step 2: Wait an additional fixed time

   After the signal is '1', use wait for 20 ns; to delay 20 nanoseconds before continuing.

3. Final Answer:

   wait until ready = '1'; wait for 20 ns; -> Option A

4. Quick Check:

   Condition wait then fixed wait = wait until ready = '1'; wait for 20 ns; [OK]

Hint: Wait for condition first, then fixed delay. [OK]

Common Mistakes:

• Reversing the order of waits.
• Using 'wait on' without condition.
• Missing single quotes around '1'.