Simulation time control in VHDL - Mini Project: Build & Apply

Simulation time control

📖 Scenario: You are working on a digital circuit simulation using VHDL. You want to control how long the simulation runs to observe the behavior of your design.

🎯 Goal: Build a simple VHDL testbench that sets a simulation stop time using wait for statements to control simulation time.

📋 What You'll Learn

Create a signal called clk initialized to '0'.

Create a constant called simulation_time with value 100 ns.

Toggle the clk signal every 10 ns using a process.

Stop the simulation after simulation_time using a wait for statement.

Print a message indicating the simulation has ended.

💡 Why This Matters

🌍 Real World

Controlling simulation time is essential when testing digital circuits to observe behavior for a specific duration.

💼 Career

Understanding simulation time control helps in verifying hardware designs efficiently before manufacturing.

1

Create clock signal

Create a signal called clk of type std_logic and initialize it to '0' inside the architecture.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavior of testbench is
signal clk : std_logic := '0';  -- Your code here
begin

end behavior;

Need a hint?

Use signal clk : std_logic := '0'; inside the architecture declaration.

2

Add simulation time constant

Add a constant called simulation_time of type time and set it to 100 ns inside the architecture.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavior of testbench is
signal clk : std_logic := '0';
constant simulation_time : time := 100 ns;  -- Your code here
begin

end behavior;

Need a hint?

Use constant simulation_time : time := 100 ns; inside the architecture declaration.

3

Create clock toggle process

Create a process called clock_process that toggles clk every 10 ns using wait for 10 ns; inside the architecture body.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavior of testbench is
signal clk : std_logic := '0';
constant simulation_time : time := 100 ns;
begin
clock_process : process
begin
    clk <= not clk;
    wait for 10 ns;  -- Your code here
end process;

end behavior;

Need a hint?

Create a process that toggles clk and waits 10 ns each time.

4

Control simulation time and print message

Add a process called simulation_control that waits for simulation_time and then prints "Simulation ended" using report. This will stop the simulation after the set time.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavior of testbench is
signal clk : std_logic := '0';
constant simulation_time : time := 100 ns;
begin
clock_process : process
begin
    clk <= not clk;
    wait for 10 ns;
end process;

simulation_control : process
begin
    wait for simulation_time;  -- Your code here
    report "Simulation ended";
    wait;
end process;

end behavior;

Need a hint?

Use a process that waits for simulation_time, then uses report to print the message and stops with wait;.