Simulation time control in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to wait for 10 ns in a VHDL testbench.

VHDL

wait for [1];

Drag options to blanks, or click blank then click option'

A10 ns

B10 ps

C100 ns

D1 us

Attempts:

3 left

💡 Hint

Common Mistakes

Using incorrect time units like ps or us when ns is required.

Omitting the time unit after the number.

The wait for statement pauses the simulation for the specified time. Here, 10 ns waits for 10 nanoseconds.

2fill in blank

medium

Complete the code to wait until the signal clk rises in a VHDL process.

VHDL

wait until [1] = '1' and clk'event;

Drag options to blanks, or click blank then click option'

Areset

Bclk

Cdata

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using a signal other than clk in the wait condition.

Forgetting to include clk'event to detect the edge.

The wait until statement pauses simulation until the condition is true. Here, it waits for the rising edge of clk.

3fill in blank

hard

Fix the error in the code to wait for 5 clock cycles of clk.

VHDL

for i in 1 to 5 loop
    wait until [1] = '1' and clk'event;
end loop;

Drag options to blanks, or click blank then click option'

Aenable

Breset

Cclk

Ddata

Attempts:

3 left

💡 Hint

Common Mistakes

Using a wrong signal in the wait condition.

Not including clk'event to detect the edge.

The loop waits for the rising edge of clk 5 times. The condition must check clk signal.

4fill in blank

hard

Fill both blanks to create a process that waits for 20 ns, then waits for a rising edge of clk.

VHDL

process
begin
    wait for [1];
    wait until [2] = '1' and clk'event;
end process;

Drag options to blanks, or click blank then click option'

A20 ns

Bclk

Creset

D10 ns

Attempts:

3 left

💡 Hint

Common Mistakes

Swapping the order of waits.

Using wrong signal names in the wait until condition.

The process first waits for 20 nanoseconds, then waits for the rising edge of clk.

5fill in blank

hard

Fill all three blanks to create a loop that waits for 10 ns, then waits for a rising edge of clk, repeated 3 times.

VHDL

process
begin
    for i in 1 to [1] loop
        wait for [2];
        wait until [3] = '1' and clk'event;
    end loop;
end process;

Drag options to blanks, or click blank then click option'

A5

B10 ns

Cclk

D3

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong loop count.

Using incorrect time units.

Using wrong signal in the wait until condition.

The loop runs 3 times, each time waiting 10 ns then waiting for the rising edge of clk.