Simulation time control in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to wait for 10 ns in a VHDL testbench.

VHDL

wait for [1];

Drag options to blanks, or click blank then click option'

A10 ns

B10 ps

C100 ns

D1 us

Attempts:

3 left

💡 Hint

Common Mistakes

Using incorrect time units like ps or us when ns is required.

Omitting the time unit after the number.

The wait for statement pauses the simulation for the specified time. Here, 10 ns waits for 10 nanoseconds.

2fill in blank

medium

Complete the code to wait until the signal clk rises in a VHDL process.

VHDL

wait until [1] = '1' and clk'event;

Drag options to blanks, or click blank then click option'

Areset

Bclk

Cdata

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using a signal other than clk in the wait condition.

Forgetting to include clk'event to detect the edge.

The wait until statement pauses simulation until the condition is true. Here, it waits for the rising edge of clk.

3fill in blank

hard

Fix the error in the code to wait for 5 clock cycles of clk.

VHDL

for i in 1 to 5 loop
    wait until [1] = '1' and clk'event;
end loop;

Drag options to blanks, or click blank then click option'

Aenable

Breset

Cclk

Ddata

Attempts:

3 left

💡 Hint

Common Mistakes

Using a wrong signal in the wait condition.

Not including clk'event to detect the edge.

The loop waits for the rising edge of clk 5 times. The condition must check clk signal.

4fill in blank

hard

Fill both blanks to create a process that waits for 20 ns, then waits for a rising edge of clk.

VHDL

process
begin
    wait for [1];
    wait until [2] = '1' and clk'event;
end process;

Drag options to blanks, or click blank then click option'

A20 ns

Bclk

Creset

D10 ns

Attempts:

3 left

💡 Hint

Common Mistakes

Swapping the order of waits.

Using wrong signal names in the wait until condition.

The process first waits for 20 nanoseconds, then waits for the rising edge of clk.

5fill in blank

hard

Fill all three blanks to create a loop that waits for 10 ns, then waits for a rising edge of clk, repeated 3 times.

VHDL

process
begin
    for i in 1 to [1] loop
        wait for [2];
        wait until [3] = '1' and clk'event;
    end loop;
end process;

Drag options to blanks, or click blank then click option'

A5

B10 ns

Cclk

D3

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong loop count.

Using incorrect time units.

Using wrong signal in the wait until condition.

The loop runs 3 times, each time waiting 10 ns then waiting for the rising edge of clk.

Practice

1. What does the VHDL statement wait for 10 ns; do in a testbench?

easy

A. Pauses the simulation for 10 nanoseconds before continuing.

B. Waits until a signal changes value.

C. Waits until a condition becomes true.

D. Ends the simulation immediately.

Solution

1. Step 1: Understand the wait for statement

   The wait for statement pauses the simulation for a fixed amount of time.

2. Step 2: Apply to the given time

   Here, it pauses for 10 nanoseconds before continuing the simulation.

3. Final Answer:

   Pauses the simulation for 10 nanoseconds before continuing. -> Option A

4. Quick Check:

   wait for 10 ns; = Pause 10 ns [OK]

Hint: Remember: 'wait for' pauses fixed time, not conditions. [OK]

Common Mistakes:

• Confusing 'wait for' with 'wait until' or 'wait on'.
• Thinking it waits for a signal change.
• Assuming it ends simulation.

2. Which of the following is the correct syntax to wait until signal clk becomes '1' in VHDL?

easy

A. wait for clk = '1';

B. wait on clk = '1';

C. wait until clk = '1';

D. wait clk = '1';

Solution

1. Step 1: Identify correct wait syntax for condition

   The correct syntax to wait for a condition is wait until condition;.

2. Step 2: Apply to signal clk equals '1'

   So, wait until clk = '1'; waits until clk becomes '1'.

3. Final Answer:

   wait until clk = '1'; -> Option C

4. Quick Check:

   Condition wait = wait until [OK]

Hint: Use 'wait until' for conditions, not 'wait for' or 'wait on'. [OK]

Common Mistakes:

• Using 'wait for' with a condition instead of time.
• Using 'wait on' incorrectly with a condition.
• Omitting 'until' keyword.

3. Consider the following VHDL testbench snippet:

signal clk : std_logic := '0';
begin
  clk_process: process
  begin
    clk <= '0';
    wait for 5 ns;
    clk <= '1';
    wait for 5 ns;
  end process;

What is the total time for one full clock cycle of clk?

medium

A. 5 ns

B. 15 ns

C. 20 ns

D. 10 ns

Solution

1. Step 1: Analyze the clock toggling times

   The clock is set to '0', then waits 5 ns, then set to '1', then waits 5 ns.

2. Step 2: Calculate total cycle time

   One full cycle is from '0' to '1' and back to '0', which takes 5 ns + 5 ns = 10 ns.

3. Final Answer:

   10 ns -> Option D

4. Quick Check:

   5 ns + 5 ns = 10 ns [OK]

Hint: Add all wait times between signal changes for full cycle. [OK]

Common Mistakes:

• Counting only one wait period.
• Confusing signal assignments with wait times.
• Ignoring that both waits add up.

4. Identify the error in this VHDL wait statement:

wait until clk = 1;

medium

A. Missing semicolon at the end.

B. Signal value should be in single quotes: '1'.

C. Cannot use 'wait until' with signals.

D. The statement should be 'wait for clk = 1;'.

Solution

1. Step 1: Check signal value syntax

   In VHDL, std_logic values must be in single quotes, e.g., '1', not 1.

2. Step 2: Confirm correct usage of 'wait until'

   The syntax wait until clk = '1'; is correct; only the quotes are missing.

3. Final Answer:

   Signal value should be in single quotes: '1'. -> Option B

4. Quick Check:

   std_logic values need single quotes [OK]

Hint: Use single quotes for std_logic values in conditions. [OK]

Common Mistakes:

• Using numeric 1 instead of character '1'.
• Confusing 'wait until' with 'wait for'.
• Omitting semicolon (though not the main error here).

5. You want to create a testbench process that waits for a signal ready to become '1', then waits an additional 20 ns before starting the next operation. Which sequence of wait statements correctly achieves this?

hard

A. wait until ready = '1'; wait for 20 ns;

B. wait for 20 ns; wait until ready = '1';

C. wait on ready; wait for 20 ns;

D. wait until ready = 1 and wait for 20 ns;

Solution

1. Step 1: Wait for the signal ready to become '1'

   The correct syntax is wait until ready = '1'; to pause until the signal is '1'.

2. Step 2: Wait an additional fixed time

   After the signal is '1', use wait for 20 ns; to delay 20 nanoseconds before continuing.

3. Final Answer:

   wait until ready = '1'; wait for 20 ns; -> Option A

4. Quick Check:

   Condition wait then fixed wait = wait until ready = '1'; wait for 20 ns; [OK]

Hint: Wait for condition first, then fixed delay. [OK]

Common Mistakes:

• Reversing the order of waits.
• Using 'wait on' without condition.
• Missing single quotes around '1'.