Simulation time control in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output time after this wait statement?

Consider the following VHDL process snippet:

process
begin
  wait for 10 ns;
  report "Checkpoint reached";
  wait for 5 ns;
  report "End of process";
  wait;
end process;

Assuming simulation starts at time 0 ns, what is the simulation time when the message "End of process" is reported?

VHDL

process
begin
  wait for 10 ns;
  report "Checkpoint reached";
  wait for 5 ns;
  report "End of process";
  wait;
end process;

A 0 ns

B 10 ns

C 5 ns

D 15 ns

💡 Hint

Add the wait times sequentially to find the total simulation time before the second report.

The process waits 10 ns first, then reports, then waits another 5 ns before the second report. So total time before "End of process" is 10 ns + 5 ns = 15 ns.

❓ Predict Output

intermediate

What happens if you use 'wait until clk = '1'' in a process?

Given the following VHDL process:

process
begin
  wait until clk = '1';
  report "Rising edge detected";
end process;

Assuming clk is a clock signal toggling every 10 ns starting at '0' at time 0, what is the simulation time when the report is first printed?

VHDL

process
begin
  wait until clk = '1';
  report "Rising edge detected";
end process;

A 10 ns

B 20 ns

C 5 ns

D 0 ns

💡 Hint

The signal clk starts at '0' and toggles every 10 ns, so the first time it becomes '1' is at 10 ns.

Since clk starts at '0' at time 0 and toggles every 10 ns, it becomes '1' at 10 ns. The wait until statement resumes at that time.

❓ Predict Output

advanced

What is the simulation time after multiple wait statements with delta delays?

Analyze this VHDL process:

process
begin
  wait for 0 ns;
  report "First report";
  wait for 0 ns;
  report "Second report";
  wait;
end process;

What is the simulation time when "Second report" is printed?

VHDL

process
begin
  wait for 0 ns;
  report "First report";
  wait for 0 ns;
  report "Second report";
  wait;
end process;

A 0 ns (different delta cycles)

B 0 ns (same delta cycle)

C 1 ns

D Undefined

💡 Hint

Wait for 0 ns advances simulation by delta cycles, not real time.

Each 'wait for 0 ns' advances simulation by one delta cycle without advancing real time. So both reports occur at simulation time 0 ns but in different delta cycles.

❓ Predict Output

advanced

What error occurs with conflicting wait statements in a process?

Consider this VHDL process:

process
begin
  wait for 10 ns;
  wait until clk = '1';
  wait;
end process;

What happens when you simulate this process?

VHDL

process
begin
  wait for 10 ns;
  wait until clk = '1';
  wait;
end process;

A Simulation error: multiple wait statements in one process

B Simulation runs normally, waiting 10 ns then until clk = '1'

C Process suspends indefinitely after first wait

D Simulation warning but continues

💡 Hint

Multiple wait statements are allowed sequentially in a process.

VHDL allows multiple wait statements in a process. The process waits 10 ns, then waits until clk = '1', then waits indefinitely.

🧠 Conceptual

expert

How does 'wait for 0 ns' affect simulation scheduling?

In VHDL simulation, what is the effect of using 'wait for 0 ns' inside a process?
Choose the most accurate description.

A It advances simulation time by one nanosecond

B It causes an immediate process termination

C It advances simulation by one delta cycle without advancing real time

D It causes a syntax error because zero time is invalid

💡 Hint

Think about how zero-time waits affect event scheduling in VHDL.

'wait for 0 ns' advances the simulation by one delta cycle, allowing other processes to run, but does not advance the actual simulation time.