Simulation time control in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output time after this wait statement?

Consider the following VHDL process snippet:

process
begin
  wait for 10 ns;
  report "Checkpoint reached";
  wait for 5 ns;
  report "End of process";
  wait;
end process;

Assuming simulation starts at time 0 ns, what is the simulation time when the message "End of process" is reported?

VHDL

process
begin
  wait for 10 ns;
  report "Checkpoint reached";
  wait for 5 ns;
  report "End of process";
  wait;
end process;

A 0 ns

B 10 ns

C 5 ns

D 15 ns

💡 Hint

Add the wait times sequentially to find the total simulation time before the second report.

The process waits 10 ns first, then reports, then waits another 5 ns before the second report. So total time before "End of process" is 10 ns + 5 ns = 15 ns.

❓ Predict Output

intermediate

What happens if you use 'wait until clk = '1'' in a process?

Given the following VHDL process:

process
begin
  wait until clk = '1';
  report "Rising edge detected";
end process;

Assuming clk is a clock signal toggling every 10 ns starting at '0' at time 0, what is the simulation time when the report is first printed?

VHDL

process
begin
  wait until clk = '1';
  report "Rising edge detected";
end process;

A 10 ns

B 20 ns

C 5 ns

D 0 ns

💡 Hint

The signal clk starts at '0' and toggles every 10 ns, so the first time it becomes '1' is at 10 ns.

Since clk starts at '0' at time 0 and toggles every 10 ns, it becomes '1' at 10 ns. The wait until statement resumes at that time.

❓ Predict Output

advanced

What is the simulation time after multiple wait statements with delta delays?

Analyze this VHDL process:

process
begin
  wait for 0 ns;
  report "First report";
  wait for 0 ns;
  report "Second report";
  wait;
end process;

What is the simulation time when "Second report" is printed?

VHDL

process
begin
  wait for 0 ns;
  report "First report";
  wait for 0 ns;
  report "Second report";
  wait;
end process;

A 0 ns (different delta cycles)

B 0 ns (same delta cycle)

C 1 ns

D Undefined

💡 Hint

Wait for 0 ns advances simulation by delta cycles, not real time.

Each 'wait for 0 ns' advances simulation by one delta cycle without advancing real time. So both reports occur at simulation time 0 ns but in different delta cycles.

❓ Predict Output

advanced

What error occurs with conflicting wait statements in a process?

Consider this VHDL process:

process
begin
  wait for 10 ns;
  wait until clk = '1';
  wait;
end process;

What happens when you simulate this process?

VHDL

process
begin
  wait for 10 ns;
  wait until clk = '1';
  wait;
end process;

A Simulation error: multiple wait statements in one process

B Simulation runs normally, waiting 10 ns then until clk = '1'

C Process suspends indefinitely after first wait

D Simulation warning but continues

💡 Hint

Multiple wait statements are allowed sequentially in a process.

VHDL allows multiple wait statements in a process. The process waits 10 ns, then waits until clk = '1', then waits indefinitely.

🧠 Conceptual

expert

How does 'wait for 0 ns' affect simulation scheduling?

In VHDL simulation, what is the effect of using 'wait for 0 ns' inside a process?
Choose the most accurate description.

A It advances simulation time by one nanosecond

B It causes an immediate process termination

C It advances simulation by one delta cycle without advancing real time

D It causes a syntax error because zero time is invalid

💡 Hint

Think about how zero-time waits affect event scheduling in VHDL.

'wait for 0 ns' advances the simulation by one delta cycle, allowing other processes to run, but does not advance the actual simulation time.

Practice

1. What does the VHDL statement wait for 10 ns; do in a testbench?

easy

A. Pauses the simulation for 10 nanoseconds before continuing.

B. Waits until a signal changes value.

C. Waits until a condition becomes true.

D. Ends the simulation immediately.

Solution

1. Step 1: Understand the wait for statement

   The wait for statement pauses the simulation for a fixed amount of time.

2. Step 2: Apply to the given time

   Here, it pauses for 10 nanoseconds before continuing the simulation.

3. Final Answer:

   Pauses the simulation for 10 nanoseconds before continuing. -> Option A

4. Quick Check:

   wait for 10 ns; = Pause 10 ns [OK]

Hint: Remember: 'wait for' pauses fixed time, not conditions. [OK]

Common Mistakes:

• Confusing 'wait for' with 'wait until' or 'wait on'.
• Thinking it waits for a signal change.
• Assuming it ends simulation.

2. Which of the following is the correct syntax to wait until signal clk becomes '1' in VHDL?

easy

A. wait for clk = '1';

B. wait on clk = '1';

C. wait until clk = '1';

D. wait clk = '1';

Solution

1. Step 1: Identify correct wait syntax for condition

   The correct syntax to wait for a condition is wait until condition;.

2. Step 2: Apply to signal clk equals '1'

   So, wait until clk = '1'; waits until clk becomes '1'.

3. Final Answer:

   wait until clk = '1'; -> Option C

4. Quick Check:

   Condition wait = wait until [OK]

Hint: Use 'wait until' for conditions, not 'wait for' or 'wait on'. [OK]

Common Mistakes:

• Using 'wait for' with a condition instead of time.
• Using 'wait on' incorrectly with a condition.
• Omitting 'until' keyword.

3. Consider the following VHDL testbench snippet:

signal clk : std_logic := '0';
begin
  clk_process: process
  begin
    clk <= '0';
    wait for 5 ns;
    clk <= '1';
    wait for 5 ns;
  end process;

What is the total time for one full clock cycle of clk?

medium

A. 5 ns

B. 15 ns

C. 20 ns

D. 10 ns

Solution

1. Step 1: Analyze the clock toggling times

   The clock is set to '0', then waits 5 ns, then set to '1', then waits 5 ns.

2. Step 2: Calculate total cycle time

   One full cycle is from '0' to '1' and back to '0', which takes 5 ns + 5 ns = 10 ns.

3. Final Answer:

   10 ns -> Option D

4. Quick Check:

   5 ns + 5 ns = 10 ns [OK]

Hint: Add all wait times between signal changes for full cycle. [OK]

Common Mistakes:

• Counting only one wait period.
• Confusing signal assignments with wait times.
• Ignoring that both waits add up.

4. Identify the error in this VHDL wait statement:

wait until clk = 1;

medium

A. Missing semicolon at the end.

B. Signal value should be in single quotes: '1'.

C. Cannot use 'wait until' with signals.

D. The statement should be 'wait for clk = 1;'.

Solution

1. Step 1: Check signal value syntax

   In VHDL, std_logic values must be in single quotes, e.g., '1', not 1.

2. Step 2: Confirm correct usage of 'wait until'

   The syntax wait until clk = '1'; is correct; only the quotes are missing.

3. Final Answer:

   Signal value should be in single quotes: '1'. -> Option B

4. Quick Check:

   std_logic values need single quotes [OK]

Hint: Use single quotes for std_logic values in conditions. [OK]

Common Mistakes:

• Using numeric 1 instead of character '1'.
• Confusing 'wait until' with 'wait for'.
• Omitting semicolon (though not the main error here).

5. You want to create a testbench process that waits for a signal ready to become '1', then waits an additional 20 ns before starting the next operation. Which sequence of wait statements correctly achieves this?

hard

A. wait until ready = '1'; wait for 20 ns;

B. wait for 20 ns; wait until ready = '1';

C. wait on ready; wait for 20 ns;

D. wait until ready = 1 and wait for 20 ns;

Solution

1. Step 1: Wait for the signal ready to become '1'

   The correct syntax is wait until ready = '1'; to pause until the signal is '1'.

2. Step 2: Wait an additional fixed time

   After the signal is '1', use wait for 20 ns; to delay 20 nanoseconds before continuing.

3. Final Answer:

   wait until ready = '1'; wait for 20 ns; -> Option A

4. Quick Check:

   Condition wait then fixed wait = wait until ready = '1'; wait for 20 ns; [OK]

Hint: Wait for condition first, then fixed delay. [OK]

Common Mistakes:

• Reversing the order of waits.
• Using 'wait on' without condition.
• Missing single quotes around '1'.