Shift operators in VHDL - Step-by-Step Execution

Concept Flow - Shift operators

Input Vector

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Select Shift Type

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Shift Left

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Shift Bits by N Positions

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Output Shifted Vector

The input vector is shifted left or right by a specified number of positions, producing a new shifted vector as output.

Execution Sample

VHDL

signal data_in : std_logic_vector(7 downto 0) := "10110011";
signal data_out : std_logic_vector(7 downto 0);

-- Shift left by 2
 data_out <= data_in sll 2;

This code shifts the 8-bit vector data_in left by 2 positions and stores the result in data_out.

Execution Table

Step	Operation	Input Vector	Shift Amount	Result Vector	Explanation
1	Initial value	10110011	N/A	10110011	Starting vector before shift
2	Shift left by 2	10110011	2	11001100	Bits shifted left 2 places, zeros fill right
3	Shift right by 3	10110011	3	00010110	Bits shifted right 3 places, zeros fill left
4	Shift left by 0	10110011	0	10110011	Shift by zero leaves vector unchanged
5	Shift right by 8	10110011	8	00000000	Shift by full length results in all zeros

💡 All shifts complete; output vectors show shifted results with zeros filling vacated bits.

Variable Tracker

Variable	Start	After Shift Left 2	After Shift Right 3	After Shift Left 0	After Shift Right 8
data_in	10110011	10110011	10110011	10110011	10110011
data_out	undefined	11001100	00010110	10110011	00000000

Key Moments - 3 Insights

Why do zeros fill in the bits when shifting?

In VHDL shift operators, when bits move out of the vector range, zeros fill the empty positions to keep the vector size constant, as shown in execution_table rows 2 and 3.

What happens if the shift amount is zero?

If the shift amount is zero, the vector remains unchanged, as seen in execution_table row 4 where the output equals the input.

Why does shifting right by the vector length produce all zeros?

Shifting right by the full vector length moves all bits out, leaving only zeros, demonstrated in execution_table row 5.

Visual Quiz - 3 Questions

Look at the execution_table, what is data_out after shifting left by 2?

A 00010110

B 11001100

C 10110011

D 00000000

💡 Hint

Check execution_table row 2 under Result Vector.

At which step does shifting right produce '00010110'?

A Step 3

B Step 2

C Step 4

D Step 5

💡 Hint

Look at execution_table row 3 for the Result Vector.

If we shift left by 8 on an 8-bit vector, what would data_out be?

A Original vector unchanged

B Vector shifted left by 1

C All zeros

D Vector shifted right by 8

💡 Hint

Refer to the pattern in execution_table row 5 for full-length shifts.

Concept Snapshot

Shift operators in VHDL move bits left (sll) or right (srl).
Bits shifted out are lost; zeros fill the empty positions.
Syntax: result <= input_vector sll n; or srl n;
Shift amount n must be integer.
Shifting by zero leaves vector unchanged.
Shifting by vector length results in all zeros.

Full Transcript

This visual execution trace shows how VHDL shift operators work on an 8-bit vector. The vector is shifted left or right by a given number of positions. When bits move out of the vector, zeros fill the empty spots to keep the size the same. For example, shifting left by 2 moves bits two places left and adds zeros on the right. Shifting right by 3 moves bits three places right and adds zeros on the left. Shifting by zero does not change the vector. Shifting by the full vector length results in all zeros. The variable tracker shows how data_in stays the same while data_out changes after each shift. Key moments clarify why zeros fill in and what happens with zero or full-length shifts. The quiz questions help check understanding by referencing the execution steps and results.