Shift operators in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this VHDL shift operation?

Given the following VHDL code snippet, what is the value of result after execution?

VHDL

signal input_val : std_logic_vector(7 downto 0) := "00011011";
signal result : std_logic_vector(7 downto 0);

begin
  result <= input_val sll 2;

A "01101100"

B "00011011"

C "00110110"

D "11011000"

💡 Hint

Remember that 'sll' shifts bits to the left and fills with zeros on the right.

The 'sll 2' shifts the bits of '00011011' two places to the left, adding two zeros on the right, resulting in '01101100'.

❓ Predict Output

intermediate

What is the result of this right shift in VHDL?

Consider this VHDL code. What is the value of output_val after the shift?

VHDL

signal input_val : std_logic_vector(7 downto 0) := "10110010";
signal output_val : std_logic_vector(7 downto 0);

begin
  output_val <= input_val srl 3;

A "11001000"

B "10110010"

C "00010110"

D "00010111"

💡 Hint

The 'srl' operator shifts bits right and fills with zeros on the left.

Shifting '10110010' right by 3 bits with 'srl' results in '00010110'.

🔧 Debug

advanced

Identify the error in this VHDL shift operation

What error will this VHDL code produce when compiled?

VHDL

signal data : std_logic_vector(7 downto 0) := "11110000";
signal shifted : std_logic_vector(7 downto 0);

begin
  shifted <= data sra 2;

A Type mismatch error: shifted and data have different sizes

B Syntax error: 'sra' cannot be used with std_logic_vector

C No error, result is "11111100"

D Runtime error: shift amount too large

💡 Hint

Check the type compatibility of the 'sra' operator in VHDL.

'sra' is not defined for std_logic_vector in standard VHDL packages; it is defined for signed and unsigned types. Using 'sra' with std_logic_vector will cause a compilation error.

🧠 Conceptual

advanced

What is the difference between 'srl' and 'sra' in VHDL?

Choose the correct explanation of the difference between the 'srl' and 'sra' shift operators in VHDL.

A 'srl' and 'sra' both shift left but differ in fill bits.

B 'srl' shifts bits left; 'sra' shifts bits right filling with zeros.

C 'srl' shifts right preserving the sign bit; 'sra' shifts right filling with zeros.

D 'srl' shifts bits right filling with zeros; 'sra' shifts right preserving the sign bit for signed types.

💡 Hint

Think about how signed numbers behave when shifted right.

'srl' is a logical right shift filling with zeros, while 'sra' is an arithmetic right shift that preserves the sign bit for signed types.

❓ Predict Output

expert

What is the output of this combined shift operation in VHDL?

Given the following VHDL code, what is the final value of final_val?

VHDL

signal val : std_logic_vector(7 downto 0) := "10011100";
signal final_val : std_logic_vector(7 downto 0);

begin
  final_val <= (val sll 1) srl 2;

A "00001110"

B "00100111"

C "01001110"

D "10011100"

💡 Hint

Apply the shifts step by step: first left shift by 1, then right shift by 2.

First, 'val sll 1' shifts '10011100' left by 1 to '00111000' (leftmost bit lost, zero added right). Then shifting this result right by 2 with 'srl' gives '00001110'.

Practice

1. What does the shift_left operator do in VHDL?

easy

A. Inverts all bits in the vector

B. Moves bits to the left, filling with zeros on the right

C. Rotates bits without changing their order

D. Moves bits to the right, filling with zeros on the left

Solution

1. Step 1: Understand the shift_left operator

   The shift_left operator moves all bits in a vector to the left by a specified number of positions.

2. Step 2: Identify what fills the empty positions

   When bits move left, zeros fill the rightmost positions to keep the vector size constant.

3. Final Answer:

   Moves bits to the left, filling with zeros on the right -> Option B

4. Quick Check:

   shift_left = left shift with zero fill [OK]

Hint: Left shift moves bits left, adds zeros on right [OK]

Common Mistakes:

• Confusing shift_left with shift_right
• Thinking bits rotate instead of filling zeros
• Assuming bits are inverted

2. Which of the following is the correct syntax to shift a 8-bit std_logic_vector data 3 bits to the right in VHDL?

easy

A. data <= shift_right(data, 3);

B. data <= shift_left(data, 3);

C. data <= data >> 3;

D. data <= shift(data, -3);

Solution

1. Step 1: Identify the correct shift function for right shift

   In VHDL, shift_right is used to shift bits to the right.

2. Step 2: Check the syntax for shifting

   The syntax is variable <= shift_right(variable, number_of_bits); so data <= shift_right(data, 3); is correct.

3. Final Answer:

   data <= shift_right(data, 3); -> Option A

4. Quick Check:

   shift_right(data, 3) is correct syntax [OK]

Hint: Use shift_right(variable, count) to shift right [OK]

Common Mistakes:

• Using shift_left instead of shift_right
• Using C-style operators like >> which are invalid in VHDL
• Using negative shift counts

3. Given the VHDL code:

signal data : std_logic_vector(7 downto 0) := "00011011";
signal result : std_logic_vector(7 downto 0);

result <= shift_left(data, 2);

What is the value of result after the shift?

medium

A. "01101100"

B. "11011000"

C. "00011000"

D. "01100000"

Solution

1. Step 1: Write the original bits and shift left by 2

   Original data: 00011011
   Shift left by 2 moves bits left 2 places: 01100000 (last two bits become zeros)

2. Step 2: Confirm the shifted bits and zero fill

   Bits shifted left: 0 0 0 1 1 0 1 1
   After shift left 2: 0 1 1 0 0 0 0 0

3. Final Answer:

   "01100000" -> Option D

4. Quick Check:

   shift_left("00011011", 2) = "01100000" [OK]

Hint: Shift left moves bits left, add zeros on right [OK]

Common Mistakes:

• Forgetting to add zeros on right
• Shifting bits right instead of left
• Miscounting bit positions

4. Consider this VHDL snippet:

signal data : std_logic_vector(7 downto 0) := "10101010";
signal result : std_logic_vector(7 downto 0);

result <= shift_right(data, 3);

But the output is unexpected. What is the likely error?

medium

A. Using shift_left instead of shift_right

B. Assigning to signal instead of variable

C. Using shift_right on std_logic_vector without numeric_std library

D. Incorrect bit width of result signal

Solution

1. Step 1: Understand shift_right requirements

   The shift_right function requires the numeric_std library for std_logic_vector operations.

2. Step 2: Identify missing library causing unexpected output

   If numeric_std is not included, shift_right may not work properly on std_logic_vector, causing wrong results.

3. Final Answer:

   Using shift_right on std_logic_vector without numeric_std library -> Option C

4. Quick Check:

   numeric_std needed for shift_right on std_logic_vector [OK]

Hint: Include numeric_std for shift_right on std_logic_vector [OK]

Common Mistakes:

• Forgetting to include numeric_std library
• Confusing shift_left and shift_right
• Assuming signals behave like variables

5. You want to multiply an 8-bit unsigned number num by 8 using shift operators in VHDL. Which expression correctly does this?

hard

A. result <= shift_left(num, 3);

B. result <= shift_right(num, 3);

C. result <= shift_left(num, 2);

D. result <= shift_right(num, 2);

Solution

1. Step 1: Understand multiplication by powers of two

   Multiplying by 8 is the same as multiplying by 2^3, which is shifting left by 3 bits.

2. Step 2: Choose the correct shift operator and count

   Use shift_left(num, 3) to multiply by 8 correctly.

3. Final Answer:

   result <= shift_left(num, 3); -> Option A

4. Quick Check:

   Multiply by 8 = shift_left by 3 [OK]

Hint: Multiply by 2^n with shift_left by n [OK]

Common Mistakes:

• Using shift_right instead of shift_left
• Shifting by wrong number of bits
• Confusing unsigned and signed types