Shift operators in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this VHDL shift operation?

Given the following VHDL code snippet, what is the value of result after execution?

VHDL

signal input_val : std_logic_vector(7 downto 0) := "00011011";
signal result : std_logic_vector(7 downto 0);

begin
  result <= input_val sll 2;

A "01101100"

B "00011011"

C "00110110"

D "11011000"

💡 Hint

Remember that 'sll' shifts bits to the left and fills with zeros on the right.

The 'sll 2' shifts the bits of '00011011' two places to the left, adding two zeros on the right, resulting in '01101100'.

❓ Predict Output

intermediate

What is the result of this right shift in VHDL?

Consider this VHDL code. What is the value of output_val after the shift?

VHDL

signal input_val : std_logic_vector(7 downto 0) := "10110010";
signal output_val : std_logic_vector(7 downto 0);

begin
  output_val <= input_val srl 3;

A "11001000"

B "10110010"

C "00010110"

D "00010111"

💡 Hint

The 'srl' operator shifts bits right and fills with zeros on the left.

Shifting '10110010' right by 3 bits with 'srl' results in '00010110'.

🔧 Debug

advanced

Identify the error in this VHDL shift operation

What error will this VHDL code produce when compiled?

VHDL

signal data : std_logic_vector(7 downto 0) := "11110000";
signal shifted : std_logic_vector(7 downto 0);

begin
  shifted <= data sra 2;

A Type mismatch error: shifted and data have different sizes

B Syntax error: 'sra' cannot be used with std_logic_vector

C No error, result is "11111100"

D Runtime error: shift amount too large

💡 Hint

Check the type compatibility of the 'sra' operator in VHDL.

'sra' is not defined for std_logic_vector in standard VHDL packages; it is defined for signed and unsigned types. Using 'sra' with std_logic_vector will cause a compilation error.

🧠 Conceptual

advanced

What is the difference between 'srl' and 'sra' in VHDL?

Choose the correct explanation of the difference between the 'srl' and 'sra' shift operators in VHDL.

A 'srl' and 'sra' both shift left but differ in fill bits.

B 'srl' shifts bits left; 'sra' shifts bits right filling with zeros.

C 'srl' shifts right preserving the sign bit; 'sra' shifts right filling with zeros.

D 'srl' shifts bits right filling with zeros; 'sra' shifts right preserving the sign bit for signed types.

💡 Hint

Think about how signed numbers behave when shifted right.

'srl' is a logical right shift filling with zeros, while 'sra' is an arithmetic right shift that preserves the sign bit for signed types.

❓ Predict Output

expert

What is the output of this combined shift operation in VHDL?

Given the following VHDL code, what is the final value of final_val?

VHDL

signal val : std_logic_vector(7 downto 0) := "10011100";
signal final_val : std_logic_vector(7 downto 0);

begin
  final_val <= (val sll 1) srl 2;

A "00001110"

B "00100111"

C "01001110"

D "10011100"

💡 Hint

Apply the shifts step by step: first left shift by 1, then right shift by 2.

First, 'val sll 1' shifts '10011100' left by 1 to '00111000' (leftmost bit lost, zero added right). Then shifting this result right by 2 with 'srl' gives '00001110'.