Shift operators in VHDL - Mini Project: Build & Apply

Shift Operators in VHDL

📖 Scenario: You are designing a simple digital circuit that needs to shift bits in a 4-bit input signal. This is common in hardware design for tasks like multiplying or dividing by powers of two.

🎯 Goal: Build a VHDL program that uses shift operators to shift a 4-bit input signal left and right by one position.

📋 What You'll Learn

Create a 4-bit std_logic_vector signal called input_signal with the value "1010"

Create an integer constant called shift_amount with the value 1

Use the shift left operator sll to shift input_signal left by shift_amount and store it in shifted_left

Use the shift right operator srl to shift input_signal right by shift_amount and store it in shifted_right

Print the values of shifted_left and shifted_right using report statements

💡 Why This Matters

🌍 Real World

Shift operators are used in digital circuits for tasks like multiplying or dividing numbers by powers of two, bit manipulation, and data encoding.

💼 Career

Understanding shift operators is essential for hardware engineers and FPGA designers working with VHDL to create efficient digital logic.

1

DATA SETUP: Create the 4-bit input signal

Create a 4-bit std_logic_vector signal called input_signal and set it to "1010".

VHDL

-- Create a 4-bit std_logic_vector signal called input_signal and set it to "1010"
-- Your code here

Need a hint?

Use signal input_signal : std_logic_vector(3 downto 0) := "1010"; inside the architecture.

2

CONFIGURATION: Define the shift amount

Create an integer constant called shift_amount and set it to 1 inside the architecture.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity shift_example is
end shift_example;

architecture behavior of shift_example is
    signal input_signal : std_logic_vector(3 downto 0) := "1010";
    -- Create an integer constant called shift_amount and set it to 1
    -- Your code here
begin
end behavior;

Need a hint?

Use constant shift_amount : integer := 1; inside the architecture.

3

CORE LOGIC: Apply shift operators

Create two signals called shifted_left and shifted_right of type std_logic_vector(3 downto 0). Assign shifted_left to input_signal sll shift_amount and shifted_right to input_signal srl shift_amount inside the architecture.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity shift_example is
end shift_example;

architecture behavior of shift_example is
    signal input_signal : std_logic_vector(3 downto 0) := "1010";
    constant shift_amount : integer := 1;
    -- Create signals shifted_left and shifted_right and assign shifted values
    -- Your code here
begin
end behavior;

Need a hint?

Declare shifted_left and shifted_right as signals and assign them using sll and srl operators.

4

OUTPUT: Display the shifted signals

Add report statements inside the architecture to print the values of shifted_left and shifted_right as strings.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity shift_example is
end shift_example;

architecture behavior of shift_example is
    signal input_signal : std_logic_vector(3 downto 0) := "1010";
    constant shift_amount : integer := 1;
    signal shifted_left : std_logic_vector(3 downto 0);
    signal shifted_right : std_logic_vector(3 downto 0);
begin
    shifted_left <= input_signal sll shift_amount;
    shifted_right <= input_signal srl shift_amount;
    -- Add report statements to print shifted_left and shifted_right
    -- Your code here
end behavior;

Need a hint?

Use a process to report the values of shifted_left and shifted_right using report and std_logic_vector'image.