Multiplexer design in VHDL - Step-by-Step Execution

Concept Flow - Multiplexer design in VHDL

Start

↓

Read select signal

↓

Check select value

↓

If select=0

→Output input0

↓

If select=1

→Output input1

↓

If select=2

→Output input2

↓

If select=3

→Output input3

↓

End

The multiplexer reads the select signal and outputs the corresponding input based on its value.

Execution Sample

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4to1 is
  Port ( sel : in STD_LOGIC_VECTOR(1 downto 0);
         d0, d1, d2, d3 : in STD_LOGIC;
         y : out STD_LOGIC);
end mux4to1;

This code defines a 4-to-1 multiplexer entity with 2-bit select and 4 data inputs.

Execution Table

Step	Select (sel)	Input Signals (d0,d1,d2,d3)	Condition	Output (y)
1	00	d0=0, d1=1, d2=0, d3=1	sel=00	0
2	01	d0=0, d1=1, d2=0, d3=1	sel=01	1
3	10	d0=0, d1=1, d2=0, d3=1	sel=10	0
4	11	d0=0, d1=1, d2=0, d3=1	sel=11	1
5	Other	Any	sel not in 00-11	Undefined or default

💡 Execution stops after outputting based on select signal value.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	Final
sel	00	00	01	10	11	11
d0	0	0	0	0	0	0
d1	1	1	1	1	1	1
d2	0	0	0	0	0	0
d3	1	1	1	1	1	1
y	U	0	1	0	1	1

Key Moments - 2 Insights

Why does the output change when the select signal changes?

Because the multiplexer uses the select signal to choose which input to send to the output, as shown in execution_table rows 1 to 4.

What happens if the select signal is outside the expected range?

The output becomes undefined or defaults, as shown in execution_table row 5, because the multiplexer only handles select values 00 to 11.

Visual Quiz - 3 Questions

Look at the execution table, what is the output y when sel = '10'?

A 1

B 0

C Undefined

D 3

💡 Hint

Check execution_table row 3 under Output (y).

At which step does the output y become '1' for the first time?

A Step 2

B Step 3

C Step 1

D Step 4

💡 Hint

Look at the Output (y) column in execution_table rows 1 and 2.

If d3 changes from '1' to '0', what will be the output y when sel = '11'?

A Undefined

B 1

C 0

D Depends on d0

💡 Hint

Refer to variable_tracker for d3 and output y at sel='11'.

Concept Snapshot

Multiplexer in VHDL:
- Use select signal (std_logic_vector) to choose input
- Output equals input selected by sel
- Use 'with sel select' or 'case' statement
- Handles multiple inputs, one output
- Undefined output if sel out of range

Full Transcript

This visual execution shows how a 4-to-1 multiplexer in VHDL works. The select signal chooses which input (d0 to d3) is sent to the output y. Each step changes the select signal and shows the output. If the select signal is outside 00 to 11, the output is undefined. Variables sel, d0-d3, and y change as the multiplexer selects inputs. Key moments clarify why output depends on select and what happens if select is invalid. The quiz tests understanding of output values at different select signals and input changes.

Practice

1. What is the main purpose of a multiplexer in VHDL design?

easy

A. To perform arithmetic operations on inputs

B. To store data temporarily

C. To select one input from multiple inputs and send it to the output

D. To generate clock signals

Solution

1. Step 1: Understand the function of a multiplexer

   A multiplexer chooses one input from many inputs based on selector signals.

2. Step 2: Identify the correct purpose

   It outputs the selected input to a single output line.

3. Final Answer:

   To select one input from multiple inputs and send it to the output -> Option C

4. Quick Check:

   Multiplexer = input selector [OK]

Hint: Multiplexer picks one input to output [OK]

Common Mistakes:

• Confusing multiplexer with arithmetic unit
• Thinking multiplexer stores data
• Assuming multiplexer generates clocks

2. Which of the following is the correct way to declare a 4-to-1 multiplexer selector signal in VHDL?

easy

A. signal sel : integer range 0 to 3;

B. signal sel : std_logic_vector(3 downto 0);

C. signal sel : std_logic;

D. signal sel : std_logic_vector(1 downto 0);

Solution

1. Step 1: Determine selector size for 4 inputs

   For 4 inputs, selector needs 2 bits (log2(4) = 2).

2. Step 2: Match selector declaration

   std_logic_vector(1 downto 0) is 2 bits wide, correct for 4-to-1 mux.

3. Final Answer:

   signal sel : std_logic_vector(1 downto 0); -> Option D

4. Quick Check:

   2-bit selector for 4 inputs [OK]

Hint: Selector bits = log2(number of inputs) [OK]

Common Mistakes:

• Using 4 bits for selector of 4 inputs
• Using single bit for multiple inputs
• Using integer instead of std_logic_vector

3. Given the following VHDL code for a 2-to-1 multiplexer, what will be the output y when sel = '1' and inputs are a = '0', b = '1'?

process(sel, a, b)
begin
  if sel = '0' then
    y <= a;
  else
    y <= b;
  end if;
end process;

medium

A. '1'

B. '0'

C. 'Z'

D. No output (error)

Solution

1. Step 1: Check selector value and inputs

   Selector sel = '1', inputs a = '0', b = '1'.

2. Step 2: Follow if-else logic

   If sel = '0', output y = a; else y = b. Since sel = '1', y = b = '1'.

3. Final Answer:

   '1' -> Option A

4. Quick Check:

   sel=1 outputs b=1 [OK]

Hint: If sel=1 output b else a [OK]

Common Mistakes:

• Confusing sel '0' and '1' cases
• Assuming output is 'Z' (high impedance)
• Ignoring input values

4. Identify the error in this 4-to-1 multiplexer VHDL code snippet:

process(sel, d0, d1, d2, d3)
begin
  case sel is
    when "00" => y <= d0;
    when "01" => y <= d1;
    when "10" => y <= d2;
    when others => y <= d3;
  end case;
end process;

medium

A. Selector signal sel is not declared as 2 bits wide

B. Missing sensitivity list signals

C. Using 'when others' instead of explicit cases

D. Output y is not assigned in all cases

Solution

1. Step 1: Check selector declaration

   The code uses sel as 2-bit vector ("00", "01", "10"), so sel must be declared as std_logic_vector(1 downto 0).

2. Step 2: Identify missing or incorrect declaration

   If sel is not declared as 2 bits wide, the case statement will cause errors.

3. Final Answer:

   Selector signal sel is not declared as 2 bits wide -> Option A

4. Quick Check:

   Selector width must match case values [OK]

Hint: Selector width must match case patterns [OK]

Common Mistakes:

• Forgetting to declare selector width
• Leaving out signals in sensitivity list
• Misusing 'when others' in case

5. You want to design an 8-to-1 multiplexer in VHDL using a case statement. Which of the following selector signal declarations and case statement headers is correct?

hard

A. signal sel : std_logic;
...
case sel is
when '0' => ...
when '1' => ...

B. signal sel : std_logic_vector(2 downto 0);
...
case sel is
when "000" => ...
when "111" => ...

C. signal sel : std_logic_vector(1 downto 0);
...
case sel is
when "00" => ...
when "11" => ...

D. signal sel : std_logic_vector(3 downto 0);
...
case sel is
when "0000" => ...
when "0111" => ...

Solution

1. Step 1: Determine selector size for 8 inputs

   8 inputs require 3 bits selector (log2(8) = 3), so sel must be 3 bits wide.

2. Step 2: Match selector declaration and case values

   signal sel : std_logic_vector(2 downto 0); ... case sel is when "000" => ... when "111" => ... uses std_logic_vector(2 downto 0) which is 3 bits, and case values from "000" to "111" which is correct.

3. Final Answer:

   signal sel : std_logic_vector(2 downto 0); ... case sel is when "000" => ... when "111" => ... -> Option B

4. Quick Check:

   3-bit selector for 8 inputs [OK]

Hint: Use 3-bit selector for 8 inputs [OK]

Common Mistakes:

• Using 4 bits for 8 inputs selector
• Using 1 or 2 bits for 8 inputs
• Mismatching case values and selector width