Multiplexer design in VHDL - Step-by-Step Execution

Concept Flow - Multiplexer design in VHDL

Start

↓

Read select signal

↓

Check select value

↓

If select=0

→Output input0

↓

If select=1

→Output input1

↓

If select=2

→Output input2

↓

If select=3

→Output input3

↓

End

The multiplexer reads the select signal and outputs the corresponding input based on its value.

Execution Sample

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4to1 is
  Port ( sel : in STD_LOGIC_VECTOR(1 downto 0);
         d0, d1, d2, d3 : in STD_LOGIC;
         y : out STD_LOGIC);
end mux4to1;

This code defines a 4-to-1 multiplexer entity with 2-bit select and 4 data inputs.

Execution Table

Step	Select (sel)	Input Signals (d0,d1,d2,d3)	Condition	Output (y)
1	00	d0=0, d1=1, d2=0, d3=1	sel=00	0
2	01	d0=0, d1=1, d2=0, d3=1	sel=01	1
3	10	d0=0, d1=1, d2=0, d3=1	sel=10	0
4	11	d0=0, d1=1, d2=0, d3=1	sel=11	1
5	Other	Any	sel not in 00-11	Undefined or default

💡 Execution stops after outputting based on select signal value.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	Final
sel	00	00	01	10	11	11
d0	0	0	0	0	0	0
d1	1	1	1	1	1	1
d2	0	0	0	0	0	0
d3	1	1	1	1	1	1
y	U	0	1	0	1	1

Key Moments - 2 Insights

Why does the output change when the select signal changes?

Because the multiplexer uses the select signal to choose which input to send to the output, as shown in execution_table rows 1 to 4.

What happens if the select signal is outside the expected range?

The output becomes undefined or defaults, as shown in execution_table row 5, because the multiplexer only handles select values 00 to 11.

Visual Quiz - 3 Questions

Look at the execution table, what is the output y when sel = '10'?

A 1

B 0

C Undefined

D 3

💡 Hint

Check execution_table row 3 under Output (y).

At which step does the output y become '1' for the first time?

A Step 2

B Step 3

C Step 1

D Step 4

💡 Hint

Look at the Output (y) column in execution_table rows 1 and 2.

If d3 changes from '1' to '0', what will be the output y when sel = '11'?

A Undefined

B 1

C 0

D Depends on d0

💡 Hint

Refer to variable_tracker for d3 and output y at sel='11'.

Concept Snapshot

Multiplexer in VHDL:
- Use select signal (std_logic_vector) to choose input
- Output equals input selected by sel
- Use 'with sel select' or 'case' statement
- Handles multiple inputs, one output
- Undefined output if sel out of range

Full Transcript

This visual execution shows how a 4-to-1 multiplexer in VHDL works. The select signal chooses which input (d0 to d3) is sent to the output y. Each step changes the select signal and shows the output. If the select signal is outside 00 to 11, the output is undefined. Variables sel, d0-d3, and y change as the multiplexer selects inputs. Key moments clarify why output depends on select and what happens if select is invalid. The quiz tests understanding of output values at different select signals and input changes.