Multiplexer design in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a multiplexer (MUX) in digital design?

A multiplexer is a device that selects one input from multiple inputs and forwards it to a single output line based on select signals.

beginner

In VHDL, which statement is commonly used to implement a multiplexer?

The with-select or case statement is commonly used to implement multiplexers in VHDL for clear and concise selection logic.

beginner

What is the role of the 'select' signal in a multiplexer?

The 'select' signal determines which input line is connected to the output by choosing among the multiple inputs.

intermediate

Explain the difference between a 2-to-1 and 4-to-1 multiplexer.

A 2-to-1 multiplexer selects one of 2 inputs based on 1 select bit, while a 4-to-1 multiplexer selects one of 4 inputs using 2 select bits.

intermediate

Show a simple VHDL code snippet for a 2-to-1 multiplexer using a 'with-select' statement.

Example:

with sel select
  output <= input0 when '0',
            input1 when '1',
            '0'      when others;

What does a multiplexer do?

A Stores data temporarily

B Adds two numbers

C Selects one input from many and sends it to output

D Generates clock signals

A multiplexer selects one input from multiple inputs based on select signals and outputs it.

In VHDL, which keyword is used to implement selection logic for multiplexers?

A wait

B process

C loop

D with-select

The 'with-select' statement is used for clear selection logic in multiplexers.

How many select lines are needed for a 4-to-1 multiplexer?

A 2

B 1

C 3

D 4

A 4-to-1 multiplexer requires 2 select lines to choose among 4 inputs.

Which of the following is NOT a valid input for a 2-to-1 multiplexer select line?

A '0'

B '2'

C '1'

D '0' or '1'

Select lines are binary signals and can only be '0' or '1'. '2' is invalid.

What output does a multiplexer produce when the select signal matches input 1?

A Input 1

B No output

C Both inputs

D Input 0

The multiplexer outputs the input selected by the select signal, here input 1.

Describe how a 4-to-1 multiplexer works and how you would implement it in VHDL.

Think about how select signals choose inputs and how VHDL syntax expresses this.

Explain why multiplexers are useful in digital circuits and give an example of their application.

Consider how multiplexers help manage multiple data sources.

Practice

1. What is the main purpose of a multiplexer in VHDL design?

easy

A. To perform arithmetic operations on inputs

B. To store data temporarily

C. To select one input from multiple inputs and send it to the output

D. To generate clock signals

Solution

1. Step 1: Understand the function of a multiplexer

   A multiplexer chooses one input from many inputs based on selector signals.

2. Step 2: Identify the correct purpose

   It outputs the selected input to a single output line.

3. Final Answer:

   To select one input from multiple inputs and send it to the output -> Option C

4. Quick Check:

   Multiplexer = input selector [OK]

Hint: Multiplexer picks one input to output [OK]

Common Mistakes:

• Confusing multiplexer with arithmetic unit
• Thinking multiplexer stores data
• Assuming multiplexer generates clocks

2. Which of the following is the correct way to declare a 4-to-1 multiplexer selector signal in VHDL?

easy

A. signal sel : integer range 0 to 3;

B. signal sel : std_logic_vector(3 downto 0);

C. signal sel : std_logic;

D. signal sel : std_logic_vector(1 downto 0);

Solution

1. Step 1: Determine selector size for 4 inputs

   For 4 inputs, selector needs 2 bits (log2(4) = 2).

2. Step 2: Match selector declaration

   std_logic_vector(1 downto 0) is 2 bits wide, correct for 4-to-1 mux.

3. Final Answer:

   signal sel : std_logic_vector(1 downto 0); -> Option D

4. Quick Check:

   2-bit selector for 4 inputs [OK]

Hint: Selector bits = log2(number of inputs) [OK]

Common Mistakes:

• Using 4 bits for selector of 4 inputs
• Using single bit for multiple inputs
• Using integer instead of std_logic_vector

3. Given the following VHDL code for a 2-to-1 multiplexer, what will be the output y when sel = '1' and inputs are a = '0', b = '1'?

process(sel, a, b)
begin
  if sel = '0' then
    y <= a;
  else
    y <= b;
  end if;
end process;

medium

A. '1'

B. '0'

C. 'Z'

D. No output (error)

Solution

1. Step 1: Check selector value and inputs

   Selector sel = '1', inputs a = '0', b = '1'.

2. Step 2: Follow if-else logic

   If sel = '0', output y = a; else y = b. Since sel = '1', y = b = '1'.

3. Final Answer:

   '1' -> Option A

4. Quick Check:

   sel=1 outputs b=1 [OK]

Hint: If sel=1 output b else a [OK]

Common Mistakes:

• Confusing sel '0' and '1' cases
• Assuming output is 'Z' (high impedance)
• Ignoring input values

4. Identify the error in this 4-to-1 multiplexer VHDL code snippet:

process(sel, d0, d1, d2, d3)
begin
  case sel is
    when "00" => y <= d0;
    when "01" => y <= d1;
    when "10" => y <= d2;
    when others => y <= d3;
  end case;
end process;

medium

A. Selector signal sel is not declared as 2 bits wide

B. Missing sensitivity list signals

C. Using 'when others' instead of explicit cases

D. Output y is not assigned in all cases

Solution

1. Step 1: Check selector declaration

   The code uses sel as 2-bit vector ("00", "01", "10"), so sel must be declared as std_logic_vector(1 downto 0).

2. Step 2: Identify missing or incorrect declaration

   If sel is not declared as 2 bits wide, the case statement will cause errors.

3. Final Answer:

   Selector signal sel is not declared as 2 bits wide -> Option A

4. Quick Check:

   Selector width must match case values [OK]

Hint: Selector width must match case patterns [OK]

Common Mistakes:

• Forgetting to declare selector width
• Leaving out signals in sensitivity list
• Misusing 'when others' in case

5. You want to design an 8-to-1 multiplexer in VHDL using a case statement. Which of the following selector signal declarations and case statement headers is correct?

hard

A. signal sel : std_logic;
...
case sel is
when '0' => ...
when '1' => ...

B. signal sel : std_logic_vector(2 downto 0);
...
case sel is
when "000" => ...
when "111" => ...

C. signal sel : std_logic_vector(1 downto 0);
...
case sel is
when "00" => ...
when "11" => ...

D. signal sel : std_logic_vector(3 downto 0);
...
case sel is
when "0000" => ...
when "0111" => ...

Solution

1. Step 1: Determine selector size for 8 inputs

   8 inputs require 3 bits selector (log2(8) = 3), so sel must be 3 bits wide.

2. Step 2: Match selector declaration and case values

   signal sel : std_logic_vector(2 downto 0); ... case sel is when "000" => ... when "111" => ... uses std_logic_vector(2 downto 0) which is 3 bits, and case values from "000" to "111" which is correct.

3. Final Answer:

   signal sel : std_logic_vector(2 downto 0); ... case sel is when "000" => ... when "111" => ... -> Option B

4. Quick Check:

   3-bit selector for 8 inputs [OK]

Hint: Use 3-bit selector for 8 inputs [OK]

Common Mistakes:

• Using 4 bits for 8 inputs selector
• Using 1 or 2 bits for 8 inputs
• Mismatching case values and selector width