Multiplexer design in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 2-to-1 multiplexer entity with inputs A, B, select S, and output Y.

VHDL

entity mux2to1 is
  port(
    A : in std_logic;
    B : in std_logic;
    S : in std_logic;
    Y : out [1]
  );
end mux2to1;

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Astd_logic_vector(1 downto 0)

Bstd_logic

Cinteger

Dbit_vector

Attempts:

3 left

💡 Hint

Common Mistakes

Using a vector type for a single bit output

Using integer type for signals

Using bit_vector instead of std_logic

The output Y is a single bit signal, so its type should be std_logic.

2fill in blank

medium

Complete the architecture declaration to define the multiplexer output using a conditional signal assignment.

VHDL

architecture Behavioral of mux2to1 is
begin
  Y <= [1] when S = '0' else B;
end Behavioral;

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AA

BS

CY

DB

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning Y to itself

Using S instead of A

Assigning B in both cases

The output Y should be assigned input A when select S is '0'.

3fill in blank

hard

Fix the error in the process block to correctly implement the multiplexer behavior.

VHDL

architecture Behavioral of mux2to1 is
begin
  process(A, B, S)
  begin
    if S = '1' then
      Y <= [1];
    else
      Y <= A;
    end if;
  end process;
end Behavioral;

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AB

BS

CY

DA

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning Y to itself

Assigning A instead of B

Using S as output

When select S is '1', output Y should be assigned input B.

4fill in blank

hard

Fill both blanks to complete the concurrent signal assignment for a 4-to-1 multiplexer output Y.

VHDL

Y <= [1] when S = "00" else
     [2] when S = "01" else
     '0';

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AA

BB

CC

DD

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing input signals with wrong select values

Using single quotes for multi-bit select

Assigning output to select signal

The output Y should be assigned input A when select S is "00" and input B when select S is "01".

5fill in blank

hard

Fill all three blanks to complete the process block for a 4-to-1 multiplexer using a case statement.

VHDL

process(S, A, B, C, D)
begin
  case [1] is
    when "00" => Y <= [2];
    when "01" => Y <= [3];
    when others => Y <= '0';
  end case;
end process;

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AS

BA

CB

DC

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong signal in case expression

Assigning output to wrong inputs

Missing when others clause

The case statement should check the select signal S. When S is "00", output Y equals A; when "01", output Y equals B.