Multiplexer design in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 2-to-1 multiplexer entity with inputs A, B, select S, and output Y.

VHDL

entity mux2to1 is
  port(
    A : in std_logic;
    B : in std_logic;
    S : in std_logic;
    Y : out [1]
  );
end mux2to1;

Drag options to blanks, or click blank then click option'

Astd_logic_vector(1 downto 0)

Bstd_logic

Cinteger

Dbit_vector

Attempts:

3 left

💡 Hint

Common Mistakes

Using a vector type for a single bit output

Using integer type for signals

Using bit_vector instead of std_logic

The output Y is a single bit signal, so its type should be std_logic.

2fill in blank

medium

Complete the architecture declaration to define the multiplexer output using a conditional signal assignment.

VHDL

architecture Behavioral of mux2to1 is
begin
  Y <= [1] when S = '0' else B;
end Behavioral;

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AA

BS

CY

DB

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning Y to itself

Using S instead of A

Assigning B in both cases

The output Y should be assigned input A when select S is '0'.

3fill in blank

hard

Fix the error in the process block to correctly implement the multiplexer behavior.

VHDL

architecture Behavioral of mux2to1 is
begin
  process(A, B, S)
  begin
    if S = '1' then
      Y <= [1];
    else
      Y <= A;
    end if;
  end process;
end Behavioral;

Drag options to blanks, or click blank then click option'

AB

BS

CY

DA

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning Y to itself

Assigning A instead of B

Using S as output

When select S is '1', output Y should be assigned input B.

4fill in blank

hard

Fill both blanks to complete the concurrent signal assignment for a 4-to-1 multiplexer output Y.

VHDL

Y <= [1] when S = "00" else
     [2] when S = "01" else
     '0';

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AA

BB

CC

DD

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing input signals with wrong select values

Using single quotes for multi-bit select

Assigning output to select signal

The output Y should be assigned input A when select S is "00" and input B when select S is "01".

5fill in blank

hard

Fill all three blanks to complete the process block for a 4-to-1 multiplexer using a case statement.

VHDL

process(S, A, B, C, D)
begin
  case [1] is
    when "00" => Y <= [2];
    when "01" => Y <= [3];
    when others => Y <= '0';
  end case;
end process;

Drag options to blanks, or click blank then click option'

AS

BA

CB

DC

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong signal in case expression

Assigning output to wrong inputs

Missing when others clause

The case statement should check the select signal S. When S is "00", output Y equals A; when "01", output Y equals B.

Practice

1. What is the main purpose of a multiplexer in VHDL design?

easy

A. To perform arithmetic operations on inputs

B. To store data temporarily

C. To select one input from multiple inputs and send it to the output

D. To generate clock signals

Solution

1. Step 1: Understand the function of a multiplexer

   A multiplexer chooses one input from many inputs based on selector signals.

2. Step 2: Identify the correct purpose

   It outputs the selected input to a single output line.

3. Final Answer:

   To select one input from multiple inputs and send it to the output -> Option C

4. Quick Check:

   Multiplexer = input selector [OK]

Hint: Multiplexer picks one input to output [OK]

Common Mistakes:

• Confusing multiplexer with arithmetic unit
• Thinking multiplexer stores data
• Assuming multiplexer generates clocks

2. Which of the following is the correct way to declare a 4-to-1 multiplexer selector signal in VHDL?

easy

A. signal sel : integer range 0 to 3;

B. signal sel : std_logic_vector(3 downto 0);

C. signal sel : std_logic;

D. signal sel : std_logic_vector(1 downto 0);

Solution

1. Step 1: Determine selector size for 4 inputs

   For 4 inputs, selector needs 2 bits (log2(4) = 2).

2. Step 2: Match selector declaration

   std_logic_vector(1 downto 0) is 2 bits wide, correct for 4-to-1 mux.

3. Final Answer:

   signal sel : std_logic_vector(1 downto 0); -> Option D

4. Quick Check:

   2-bit selector for 4 inputs [OK]

Hint: Selector bits = log2(number of inputs) [OK]

Common Mistakes:

• Using 4 bits for selector of 4 inputs
• Using single bit for multiple inputs
• Using integer instead of std_logic_vector

3. Given the following VHDL code for a 2-to-1 multiplexer, what will be the output y when sel = '1' and inputs are a = '0', b = '1'?

process(sel, a, b)
begin
  if sel = '0' then
    y <= a;
  else
    y <= b;
  end if;
end process;

medium

A. '1'

B. '0'

C. 'Z'

D. No output (error)

Solution

1. Step 1: Check selector value and inputs

   Selector sel = '1', inputs a = '0', b = '1'.

2. Step 2: Follow if-else logic

   If sel = '0', output y = a; else y = b. Since sel = '1', y = b = '1'.

3. Final Answer:

   '1' -> Option A

4. Quick Check:

   sel=1 outputs b=1 [OK]

Hint: If sel=1 output b else a [OK]

Common Mistakes:

• Confusing sel '0' and '1' cases
• Assuming output is 'Z' (high impedance)
• Ignoring input values

4. Identify the error in this 4-to-1 multiplexer VHDL code snippet:

process(sel, d0, d1, d2, d3)
begin
  case sel is
    when "00" => y <= d0;
    when "01" => y <= d1;
    when "10" => y <= d2;
    when others => y <= d3;
  end case;
end process;

medium

A. Selector signal sel is not declared as 2 bits wide

B. Missing sensitivity list signals

C. Using 'when others' instead of explicit cases

D. Output y is not assigned in all cases

Solution

1. Step 1: Check selector declaration

   The code uses sel as 2-bit vector ("00", "01", "10"), so sel must be declared as std_logic_vector(1 downto 0).

2. Step 2: Identify missing or incorrect declaration

   If sel is not declared as 2 bits wide, the case statement will cause errors.

3. Final Answer:

   Selector signal sel is not declared as 2 bits wide -> Option A

4. Quick Check:

   Selector width must match case values [OK]

Hint: Selector width must match case patterns [OK]

Common Mistakes:

• Forgetting to declare selector width
• Leaving out signals in sensitivity list
• Misusing 'when others' in case

5. You want to design an 8-to-1 multiplexer in VHDL using a case statement. Which of the following selector signal declarations and case statement headers is correct?

hard

A. signal sel : std_logic;
...
case sel is
when '0' => ...
when '1' => ...

B. signal sel : std_logic_vector(2 downto 0);
...
case sel is
when "000" => ...
when "111" => ...

C. signal sel : std_logic_vector(1 downto 0);
...
case sel is
when "00" => ...
when "11" => ...

D. signal sel : std_logic_vector(3 downto 0);
...
case sel is
when "0000" => ...
when "0111" => ...

Solution

1. Step 1: Determine selector size for 8 inputs

   8 inputs require 3 bits selector (log2(8) = 3), so sel must be 3 bits wide.

2. Step 2: Match selector declaration and case values

   signal sel : std_logic_vector(2 downto 0); ... case sel is when "000" => ... when "111" => ... uses std_logic_vector(2 downto 0) which is 3 bits, and case values from "000" to "111" which is correct.

3. Final Answer:

   signal sel : std_logic_vector(2 downto 0); ... case sel is when "000" => ... when "111" => ... -> Option B

4. Quick Check:

   3-bit selector for 8 inputs [OK]

Hint: Use 3-bit selector for 8 inputs [OK]

Common Mistakes:

• Using 4 bits for 8 inputs selector
• Using 1 or 2 bits for 8 inputs
• Mismatching case values and selector width