Multiplexer design in VHDL - Mini Project: Build & Apply

Multiplexer Design in VHDL

📖 Scenario: You are designing a simple digital circuit that selects one of several input signals and forwards it to a single output line. This is called a multiplexer, a common component in electronics and digital systems.

🎯 Goal: Build a 4-to-1 multiplexer in VHDL that selects one of four input bits based on a 2-bit selector and outputs the selected input.

📋 What You'll Learn

Create a VHDL entity named Mux4to1 with inputs sel (2 bits), in0, in1, in2, in3 (each 1 bit), and output out (1 bit).

Define an architecture that uses a with-select statement to assign the output based on the selector.

Test the multiplexer by assigning values to inputs and selector and observe the output.

💡 Why This Matters

🌍 Real World

Multiplexers are used in digital circuits to select data lines, saving hardware and routing signals efficiently.

💼 Career

Understanding multiplexer design in VHDL is essential for hardware engineers working on FPGA or ASIC design.

1

Create the Multiplexer Entity

Write the VHDL code to declare an entity named Mux4to1 with inputs sel as a 2-bit std_logic_vector, in0, in1, in2, in3 as std_logic, and output out as std_logic.

VHDL

-- Declare the entity Mux4to1 with inputs sel, in0, in1, in2, in3 and output out
-- Your code here

Need a hint?

Use entity and Port to declare inputs and outputs with correct types.

2

Add Architecture with with-select Statement

Write the architecture named Behavior for Mux4to1 that uses a with sel select statement to assign out to in0, in1, in2, or in3 depending on the value of sel.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux4to1 is
    Port (
        sel : in std_logic_vector(1 downto 0);
        in0 : in std_logic;
        in1 : in std_logic;
        in2 : in std_logic;
        in3 : in std_logic;
        out : out std_logic
    );
end Mux4to1;

architecture Behavior of Mux4to1 is
begin
    -- Use with-select statement to assign out
    -- Your code here
end Behavior;

Need a hint?

Use with sel select to choose output based on selector values "00", "01", "10", and "11".

3

Create a Testbench to Assign Inputs and Selector

Write a simple testbench process inside a new architecture named Testbench that declares signals for sel, in0, in1, in2, in3, and out. Assign in0 = '0', in1 = '1', in2 = '0', in3 = '1'. Then assign sel to "00", "01", "10", and "11" sequentially with a wait of 10 ns between each.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux4to1 is
    Port (
        sel : in std_logic_vector(1 downto 0);
        in0 : in std_logic;
        in1 : in std_logic;
        in2 : in std_logic;
        in3 : in std_logic;
        out : out std_logic
    );
end Mux4to1;

architecture Behavior of Mux4to1 is
begin
    with sel select
        out <= in0 when "00",
               in1 when "01",
               in2 when "10",
               in3 when "11",
               '0' when others;
end Behavior;

-- Add testbench architecture below
-- Your code here

Need a hint?

Declare signals for inputs and output. Instantiate the multiplexer entity. Use a process to assign inputs and change selector with waits.

4

Simulate and Observe Output

Run the simulation of the testbench and observe the value of out for each selector value. Print the output value after each selector assignment using a report statement inside the process.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux4to1 is
    Port (
        sel : in std_logic_vector(1 downto 0);
        in0 : in std_logic;
        in1 : in std_logic;
        in2 : in std_logic;
        in3 : in std_logic;
        out : out std_logic
    );
end Mux4to1;

architecture Behavior of Mux4to1 is
begin
    with sel select
        out  sel, in0 => in0, in1 => in1, in2 => in2, in3 => in3, out => out);

    stim_proc: process
    begin
        in0 <= '0';
        in1 <= '1';
        in2 <= '0';
        in3 <= '1';

        sel <= "00";
        wait for 10 ns;
        -- Add report statement to print output
        sel <= "01";
        wait for 10 ns;
        -- Add report statement to print output
        sel <= "10";
        wait for 10 ns;
        -- Add report statement to print output
        sel <= "11";
        wait for 10 ns;
        -- Add report statement to print output

        wait;
    end process;
end Testbench;

Need a hint?

Use report statements inside the process after each wait to print the output value.