Multiplexer design in VHDL - Mini Project: Build & Apply

Multiplexer Design in VHDL

📖 Scenario: You are designing a simple digital circuit that selects one of several input signals and forwards it to a single output line. This is called a multiplexer, a common component in electronics and digital systems.

🎯 Goal: Build a 4-to-1 multiplexer in VHDL that selects one of four input bits based on a 2-bit selector and outputs the selected input.

📋 What You'll Learn

Create a VHDL entity named Mux4to1 with inputs sel (2 bits), in0, in1, in2, in3 (each 1 bit), and output out (1 bit).

Define an architecture that uses a with-select statement to assign the output based on the selector.

Test the multiplexer by assigning values to inputs and selector and observe the output.

💡 Why This Matters

🌍 Real World

Multiplexers are used in digital circuits to select data lines, saving hardware and routing signals efficiently.

💼 Career

Understanding multiplexer design in VHDL is essential for hardware engineers working on FPGA or ASIC design.

1

Create the Multiplexer Entity

Write the VHDL code to declare an entity named Mux4to1 with inputs sel as a 2-bit std_logic_vector, in0, in1, in2, in3 as std_logic, and output out as std_logic.

VHDL

-- Declare the entity Mux4to1 with inputs sel, in0, in1, in2, in3 and output out
-- Your code here

Hint

Use entity and Port to declare inputs and outputs with correct types.

2

Add Architecture with with-select Statement

Write the architecture named Behavior for Mux4to1 that uses a with sel select statement to assign out to in0, in1, in2, or in3 depending on the value of sel.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux4to1 is
    Port (
        sel : in std_logic_vector(1 downto 0);
        in0 : in std_logic;
        in1 : in std_logic;
        in2 : in std_logic;
        in3 : in std_logic;
        out : out std_logic
    );
end Mux4to1;

architecture Behavior of Mux4to1 is
begin
    -- Use with-select statement to assign out
    -- Your code here
end Behavior;

Hint

Use with sel select to choose output based on selector values "00", "01", "10", and "11".

3

Create a Testbench to Assign Inputs and Selector

Write a simple testbench process inside a new architecture named Testbench that declares signals for sel, in0, in1, in2, in3, and out. Assign in0 = '0', in1 = '1', in2 = '0', in3 = '1'. Then assign sel to "00", "01", "10", and "11" sequentially with a wait of 10 ns between each.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux4to1 is
    Port (
        sel : in std_logic_vector(1 downto 0);
        in0 : in std_logic;
        in1 : in std_logic;
        in2 : in std_logic;
        in3 : in std_logic;
        out : out std_logic
    );
end Mux4to1;

architecture Behavior of Mux4to1 is
begin
    with sel select
        out <= in0 when "00",
               in1 when "01",
               in2 when "10",
               in3 when "11",
               '0' when others;
end Behavior;

-- Add testbench architecture below
-- Your code here

Hint

Declare signals for inputs and output. Instantiate the multiplexer entity. Use a process to assign inputs and change selector with waits.

4

Simulate and Observe Output

Run the simulation of the testbench and observe the value of out for each selector value. Print the output value after each selector assignment using a report statement inside the process.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux4to1 is
    Port (
        sel : in std_logic_vector(1 downto 0);
        in0 : in std_logic;
        in1 : in std_logic;
        in2 : in std_logic;
        in3 : in std_logic;
        out : out std_logic
    );
end Mux4to1;

architecture Behavior of Mux4to1 is
begin
    with sel select
        out  sel, in0 => in0, in1 => in1, in2 => in2, in3 => in3, out => out);

    stim_proc: process
    begin
        in0 <= '0';
        in1 <= '1';
        in2 <= '0';
        in3 <= '1';

        sel <= "00";
        wait for 10 ns;
        -- Add report statement to print output
        sel <= "01";
        wait for 10 ns;
        -- Add report statement to print output
        sel <= "10";
        wait for 10 ns;
        -- Add report statement to print output
        sel <= "11";
        wait for 10 ns;
        -- Add report statement to print output

        wait;
    end process;
end Testbench;

Hint

Use report statements inside the process after each wait to print the output value.

Practice

1. What is the main purpose of a multiplexer in VHDL design?

easy

A. To perform arithmetic operations on inputs

B. To store data temporarily

C. To select one input from multiple inputs and send it to the output

D. To generate clock signals

Solution

1. Step 1: Understand the function of a multiplexer

   A multiplexer chooses one input from many inputs based on selector signals.

2. Step 2: Identify the correct purpose

   It outputs the selected input to a single output line.

3. Final Answer:

   To select one input from multiple inputs and send it to the output -> Option C

4. Quick Check:

   Multiplexer = input selector [OK]

Hint: Multiplexer picks one input to output [OK]

Common Mistakes:

• Confusing multiplexer with arithmetic unit
• Thinking multiplexer stores data
• Assuming multiplexer generates clocks

2. Which of the following is the correct way to declare a 4-to-1 multiplexer selector signal in VHDL?

easy

A. signal sel : integer range 0 to 3;

B. signal sel : std_logic_vector(3 downto 0);

C. signal sel : std_logic;

D. signal sel : std_logic_vector(1 downto 0);

Solution

1. Step 1: Determine selector size for 4 inputs

   For 4 inputs, selector needs 2 bits (log2(4) = 2).

2. Step 2: Match selector declaration

   std_logic_vector(1 downto 0) is 2 bits wide, correct for 4-to-1 mux.

3. Final Answer:

   signal sel : std_logic_vector(1 downto 0); -> Option D

4. Quick Check:

   2-bit selector for 4 inputs [OK]

Hint: Selector bits = log2(number of inputs) [OK]

Common Mistakes:

• Using 4 bits for selector of 4 inputs
• Using single bit for multiple inputs
• Using integer instead of std_logic_vector

3. Given the following VHDL code for a 2-to-1 multiplexer, what will be the output y when sel = '1' and inputs are a = '0', b = '1'?

process(sel, a, b)
begin
  if sel = '0' then
    y <= a;
  else
    y <= b;
  end if;
end process;

medium

A. '1'

B. '0'

C. 'Z'

D. No output (error)

Solution

1. Step 1: Check selector value and inputs

   Selector sel = '1', inputs a = '0', b = '1'.

2. Step 2: Follow if-else logic

   If sel = '0', output y = a; else y = b. Since sel = '1', y = b = '1'.

3. Final Answer:

   '1' -> Option A

4. Quick Check:

   sel=1 outputs b=1 [OK]

Hint: If sel=1 output b else a [OK]

Common Mistakes:

• Confusing sel '0' and '1' cases
• Assuming output is 'Z' (high impedance)
• Ignoring input values

4. Identify the error in this 4-to-1 multiplexer VHDL code snippet:

process(sel, d0, d1, d2, d3)
begin
  case sel is
    when "00" => y <= d0;
    when "01" => y <= d1;
    when "10" => y <= d2;
    when others => y <= d3;
  end case;
end process;

medium

A. Selector signal sel is not declared as 2 bits wide

B. Missing sensitivity list signals

C. Using 'when others' instead of explicit cases

D. Output y is not assigned in all cases

Solution

1. Step 1: Check selector declaration

   The code uses sel as 2-bit vector ("00", "01", "10"), so sel must be declared as std_logic_vector(1 downto 0).

2. Step 2: Identify missing or incorrect declaration

   If sel is not declared as 2 bits wide, the case statement will cause errors.

3. Final Answer:

   Selector signal sel is not declared as 2 bits wide -> Option A

4. Quick Check:

   Selector width must match case values [OK]

Hint: Selector width must match case patterns [OK]

Common Mistakes:

• Forgetting to declare selector width
• Leaving out signals in sensitivity list
• Misusing 'when others' in case

5. You want to design an 8-to-1 multiplexer in VHDL using a case statement. Which of the following selector signal declarations and case statement headers is correct?

hard

A. signal sel : std_logic;
...
case sel is
when '0' => ...
when '1' => ...

B. signal sel : std_logic_vector(2 downto 0);
...
case sel is
when "000" => ...
when "111" => ...

C. signal sel : std_logic_vector(1 downto 0);
...
case sel is
when "00" => ...
when "11" => ...

D. signal sel : std_logic_vector(3 downto 0);
...
case sel is
when "0000" => ...
when "0111" => ...

Solution

1. Step 1: Determine selector size for 8 inputs

   8 inputs require 3 bits selector (log2(8) = 3), so sel must be 3 bits wide.

2. Step 2: Match selector declaration and case values

   signal sel : std_logic_vector(2 downto 0); ... case sel is when "000" => ... when "111" => ... uses std_logic_vector(2 downto 0) which is 3 bits, and case values from "000" to "111" which is correct.

3. Final Answer:

   signal sel : std_logic_vector(2 downto 0); ... case sel is when "000" => ... when "111" => ... -> Option B

4. Quick Check:

   3-bit selector for 8 inputs [OK]

Hint: Use 3-bit selector for 8 inputs [OK]

Common Mistakes:

• Using 4 bits for 8 inputs selector
• Using 1 or 2 bits for 8 inputs
• Mismatching case values and selector width