Multiplexer design in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of 2-to-1 Multiplexer VHDL Code

What is the output of the following 2-to-1 multiplexer VHDL code when sel = '1' and a = '0', b = '1'?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux2to1 is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           sel : in STD_LOGIC;
           y : out STD_LOGIC);
end mux2to1;

architecture Behavioral of mux2to1 is
begin
    y <= a when sel = '0' else b;
end Behavioral;

A 'X'

B '0'

C 'Z'

D '1'

💡 Hint

Remember, the output y follows input b when sel is '1'.

The multiplexer selects input b when sel = '1', so output y will be '1'.

🧠 Conceptual

intermediate

Number of Select Lines for 8-to-1 Multiplexer

How many select lines are needed to design an 8-to-1 multiplexer in VHDL?

A 8

B 4

C 3

D 1

💡 Hint

Number of select lines = log2(number of inputs).

An 8-to-1 multiplexer has 8 inputs, so select lines = log2(8) = 3.

🔧 Debug

advanced

Identify the Error in 4-to-1 Multiplexer VHDL Code

What error will the following VHDL code produce when compiled?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4to1 is
    Port ( a : in STD_LOGIC_VECTOR(3 downto 0);
           sel : in STD_LOGIC_VECTOR(1 downto 0);
           y : out STD_LOGIC);
end mux4to1;

architecture Behavioral of mux4to1 is
begin
    process(a, sel)
    begin
        case sel is
            when "00" => y <= a(0);
            when "01" => y <= a(1);
            when "10" => y <= a(2);
            when "11" => y <= a(3);
            when others => y <= '0';
        end case;
    end process;
end Behavioral;

A Syntax error: missing semicolon after end case

B Runtime error: index out of range

C No error, code compiles and works correctly

D Syntax error: missing sensitivity list in process

💡 Hint

Check the syntax of the case statement carefully.

The case statement must end with a semicolon after 'end case'. Missing it causes a syntax error.

📝 Syntax

advanced

Correct VHDL Syntax for 8-to-1 Multiplexer Output Assignment

Which option correctly assigns the output y in an 8-to-1 multiplexer using a selected input vector a and select lines sel?

A y <= a(to_integer(unsigned(sel)));

B y <= a(to_integer(sel));

C y <= a(sel & 0);

D y <= a(sel);

💡 Hint

You need to convert the select lines from std_logic_vector to integer index.

The select lines are std_logic_vector and must be converted to integer using to_integer(unsigned(sel)) to index the input vector.

🚀 Application

expert

Output of 4-to-1 Multiplexer with Mixed Inputs

Given the following VHDL code for a 4-to-1 multiplexer, what is the output y when a = "1010" and sel = "10"?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity mux4to1 is
    Port ( a : in STD_LOGIC_VECTOR(3 downto 0);
           sel : in STD_LOGIC_VECTOR(1 downto 0);
           y : out STD_LOGIC);
end mux4to1;

architecture Behavioral of mux4to1 is
begin
    y <= a(to_integer(unsigned(sel)));
end Behavioral;

A '1'

B '0'

C 'X'

D 'Z'

💡 Hint

Convert sel to integer and use it as index to select bit from a.

sel = "10" is binary 2, so output y = a(2). a = "1010" indexed from 3 downto 0 means a(2) = '0'.