Assert statement for verification in VHDL - Step-by-Step Execution

Concept Flow - Assert statement for verification

Start Simulation

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Evaluate Condition

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Continue

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Next Step

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End Simulation

The assert statement checks a condition during simulation. If true, simulation continues. If false, it reports an error and can stop or log the issue.

Execution Sample

VHDL

assert (a = b) report "Mismatch detected" severity error;

Checks if 'a' equals 'b'; if not, reports an error and stops simulation.

Execution Table

Step	Condition (a = b)	Result	Action	Simulation Status
1	True	Pass	Continue simulation	Running
2	False	Fail	Report "Mismatch detected" severity error	Error reported, simulation stops

💡 Simulation stops when condition is False and severity is error

Variable Tracker

Variable	Start	After Step 1	After Step 2
a	0	0	1
b	0	0	0

Key Moments - 2 Insights

Why does the simulation stop when the assert condition is false?

Because the severity level is set to 'error', which instructs the simulator to stop, as shown in execution_table row 2.

What happens if the assert condition is true?

The simulation continues normally without interruption, as shown in execution_table row 1.

Visual Quiz - 3 Questions

Look at the execution_table, what is the simulation status when the condition (a = b) is true?

A Running

B Error reported

C Paused

D Stopped

💡 Hint

Check the 'Simulation Status' column in execution_table row 1.

At which step does the assert statement report an error?

A Step 1

B Step 2

C Step 3

D No error reported

💡 Hint

Look at the 'Action' column in execution_table row 2.

If the severity was changed from 'error' to 'warning', what would likely happen?

A Simulation stops immediately

B Simulation restarts

C Simulation continues with a warning message

D Simulation ignores the assert

💡 Hint

Severity 'warning' usually logs a message but does not stop simulation.

Concept Snapshot

Assert statement syntax:
assert (condition) report "message" severity level;
Checks condition during simulation.
If false and severity is error, simulation stops.
If true, simulation continues.
Used for verification and debugging.

Full Transcript

The assert statement in VHDL is used to check conditions during simulation. When the condition is true, the simulation continues normally. If the condition is false, the assert reports a message and, depending on the severity level, can stop the simulation. In the example, when 'a' equals 'b', the simulation runs without interruption. When they differ, an error message is reported and the simulation stops. This helps catch design errors early during verification.