Assert statement for verification in VHDL - Step-by-Step Execution

Concept Flow - Assert statement for verification

Start Simulation

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Evaluate Condition

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Continue

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Next Step

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End Simulation

The assert statement checks a condition during simulation. If true, simulation continues. If false, it reports an error and can stop or log the issue.

Execution Sample

VHDL

assert (a = b) report "Mismatch detected" severity error;

Checks if 'a' equals 'b'; if not, reports an error and stops simulation.

Execution Table

Step	Condition (a = b)	Result	Action	Simulation Status
1	True	Pass	Continue simulation	Running
2	False	Fail	Report "Mismatch detected" severity error	Error reported, simulation stops

💡 Simulation stops when condition is False and severity is error

Variable Tracker

Variable	Start	After Step 1	After Step 2
a	0	0	1
b	0	0	0

Key Moments - 2 Insights

Why does the simulation stop when the assert condition is false?

Because the severity level is set to 'error', which instructs the simulator to stop, as shown in execution_table row 2.

What happens if the assert condition is true?

The simulation continues normally without interruption, as shown in execution_table row 1.

Visual Quiz - 3 Questions

Look at the execution_table, what is the simulation status when the condition (a = b) is true?

A Running

B Error reported

C Paused

D Stopped

💡 Hint

Check the 'Simulation Status' column in execution_table row 1.

At which step does the assert statement report an error?

A Step 1

B Step 2

C Step 3

D No error reported

💡 Hint

Look at the 'Action' column in execution_table row 2.

If the severity was changed from 'error' to 'warning', what would likely happen?

A Simulation stops immediately

B Simulation restarts

C Simulation continues with a warning message

D Simulation ignores the assert

💡 Hint

Severity 'warning' usually logs a message but does not stop simulation.

Concept Snapshot

Assert statement syntax:
assert (condition) report "message" severity level;
Checks condition during simulation.
If false and severity is error, simulation stops.
If true, simulation continues.
Used for verification and debugging.

Full Transcript

The assert statement in VHDL is used to check conditions during simulation. When the condition is true, the simulation continues normally. If the condition is false, the assert reports a message and, depending on the severity level, can stop the simulation. In the example, when 'a' equals 'b', the simulation runs without interruption. When they differ, an error message is reported and the simulation stops. This helps catch design errors early during verification.

Practice

1. What is the main purpose of the assert statement in VHDL?

easy

A. To check conditions during simulation and report errors

B. To declare variables in the design

C. To assign values to signals

D. To create loops in the code

Solution

1. Step 1: Understand the role of assert in VHDL

   The assert statement is used to verify conditions during simulation, helping catch errors early.

2. Step 2: Compare with other options

   Other options describe unrelated tasks: declaring variables, assigning signals, or looping.

3. Final Answer:

   To check conditions during simulation and report errors -> Option A

4. Quick Check:

   Assert checks conditions = To check conditions during simulation and report errors [OK]

Hint: Assert is for checking conditions during simulation [OK]

Common Mistakes:

• Confusing assert with signal assignment
• Thinking assert declares variables
• Assuming assert creates loops

2. Which of the following is the correct syntax for an assert statement in VHDL?

easy

A. assert condition, "message", severity level;

B. assert (condition) then report "message" severity level;

C. assert condition report "message" severity level;

D. assert condition report "message" severity level

Solution

1. Step 1: Recall correct assert syntax

   The correct syntax is: assert condition report "message" severity level; with a semicolon at the end.

2. Step 2: Check each option

   assert condition report "message" severity level; matches exactly. assert (condition) then report "message" severity level; has incorrect 'then'. assert condition, "message", severity level; uses commas incorrectly. assert condition report "message" severity level misses the semicolon.

3. Final Answer:

   assert condition report "message" severity level; -> Option C

4. Quick Check:

   Correct assert syntax ends with semicolon [OK]

Hint: Remember assert ends with semicolon and uses 'report' keyword [OK]

Common Mistakes:

• Omitting semicolon at the end
• Using commas instead of keywords
• Adding 'then' after condition

3. What will be the output during simulation for the following VHDL code snippet?

signal x : integer := 5;
begin
  assert x > 10 report "Value too low" severity warning;
end;

medium

A. Simulation stops with error

B. Warning message: "Value too low" is displayed

C. No message is displayed, simulation continues silently

D. Syntax error due to missing semicolon

Solution

1. Step 1: Evaluate the assert condition

   The condition x > 10 is false since x = 5.

2. Step 2: Understand severity level effect

   Severity is warning, so simulation shows a warning message but continues.

3. Final Answer:

   Warning message: "Value too low" is displayed -> Option B

4. Quick Check:

   False condition + warning severity = warning message [OK]

Hint: False assert with warning shows message but continues [OK]

Common Mistakes:

• Thinking simulation stops on warning severity
• Ignoring the severity level
• Assuming no message if condition false

4. Identify the error in this VHDL assert statement:

assert (a = b) report "Mismatch" severity error

medium

A. Missing semicolon at the end

B. Incorrect use of parentheses around condition

C. Wrong severity level keyword

D. Missing report keyword

Solution

1. Step 1: Check syntax completeness

   The assert statement must end with a semicolon; it is missing here.

2. Step 2: Verify other parts

   Parentheses around condition are allowed, severity keyword is correct, and report keyword is present.

3. Final Answer:

   Missing semicolon at the end -> Option A

4. Quick Check:

   Assert statements end with semicolon [OK]

Hint: Always end assert statements with semicolon [OK]

Common Mistakes:

• Forgetting semicolon
• Thinking parentheses are not allowed
• Confusing severity keywords

5. You want to verify that a signal data_valid is always true during simulation. Which assert statement correctly stops simulation on failure and shows an error message?

hard

A. assert data_valid report "Data invalid" severity critical;

B. assert data_valid report "Data invalid" severity warning;

C. assert not data_valid report "Data invalid" severity note;

D. assert data_valid report "Data invalid" severity error;

Solution

1. Step 1: Understand severity levels for stopping simulation

   Severity error stops simulation and reports an error message.

2. Step 2: Analyze each option

   assert data_valid report "Data invalid" severity warning; uses warning (does not stop). assert data_valid report "Data invalid" severity error; uses error (correct). assert not data_valid report "Data invalid" severity note; negates condition and uses note (no stop). assert data_valid report "Data invalid" severity critical; uses critical which is not a valid severity.

3. Final Answer:

   assert data_valid report "Data invalid" severity error; -> Option D

4. Quick Check:

   Error severity stops simulation = assert data_valid report "Data invalid" severity error; [OK]

Hint: Use severity error to stop simulation on assert failure [OK]

Common Mistakes:

• Using warning instead of error severity
• Negating condition incorrectly
• Using invalid severity keywords