Assert statement for verification in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the purpose of the assert statement in VHDL?

The assert statement is used to check conditions during simulation. It helps verify that the design behaves as expected by reporting errors or warnings if conditions fail.

beginner

How do you write a basic assert statement in VHDL?

A basic assert statement looks like this:

assert condition report "message" severity level;

It checks condition, and if false, shows message with a severity like note, warning, or error.

intermediate

What are the common severity levels used with assert in VHDL?

Common severity levels are:
- note: Informational message
- warning: Indicates a potential problem
- error: Indicates a serious problem
- failure: Stops simulation immediately

beginner

Can assert statements be used for functional verification in VHDL?

Yes, assert statements are widely used in testbenches to verify that signals and outputs meet expected conditions during simulation.

intermediate

What happens if an assert condition fails during simulation?

If the condition is false, the simulator displays the report message with the specified severity. For error or failure, simulation may stop or pause, helping catch bugs early.

What does the assert statement do in VHDL?

A Starts the simulation

B Defines a new signal

C Declares a variable

D Checks a condition and reports if false

The assert statement checks a condition and reports a message if the condition is false.

Which severity level stops the simulation immediately when an assert fails?

A failure

B warning

C error

D note

failure severity stops the simulation immediately upon assertion failure.

How do you write an assert statement that checks if signal clk is '1'?

A assert clk == 1 report "Clock is low" severity error;

B assert clk = '1' report "Clock is low" severity error;

C assert clk = 1 report "Clock is low" severity error;

D assert clk != '1' report "Clock is low" severity error;

In VHDL, single quotes are used for single bits. The correct syntax is assert clk = '1'.

Where are assert statements commonly used in VHDL?

A In testbenches for verification

B To declare ports

C To synthesize hardware

D To assign values to signals

assert statements are mainly used in testbenches to verify design behavior during simulation.

What message does an assert statement show if the condition is true?

A Error message

B Warning message

C No message

D Note message

If the condition is true, the assert statement does nothing and shows no message.

Explain how the assert statement helps in verifying VHDL designs.

Think about how you check if something is right or wrong while testing.

Write the syntax of an assert statement that reports a warning if a signal reset is not '0'.

Start with 'assert reset = '0'' then add report and severity.

Practice

1. What is the main purpose of the assert statement in VHDL?

easy

A. To check conditions during simulation and report errors

B. To declare variables in the design

C. To assign values to signals

D. To create loops in the code

Solution

1. Step 1: Understand the role of assert in VHDL

   The assert statement is used to verify conditions during simulation, helping catch errors early.

2. Step 2: Compare with other options

   Other options describe unrelated tasks: declaring variables, assigning signals, or looping.

3. Final Answer:

   To check conditions during simulation and report errors -> Option A

4. Quick Check:

   Assert checks conditions = To check conditions during simulation and report errors [OK]

Hint: Assert is for checking conditions during simulation [OK]

Common Mistakes:

• Confusing assert with signal assignment
• Thinking assert declares variables
• Assuming assert creates loops

2. Which of the following is the correct syntax for an assert statement in VHDL?

easy

A. assert condition, "message", severity level;

B. assert (condition) then report "message" severity level;

C. assert condition report "message" severity level;

D. assert condition report "message" severity level

Solution

1. Step 1: Recall correct assert syntax

   The correct syntax is: assert condition report "message" severity level; with a semicolon at the end.

2. Step 2: Check each option

   assert condition report "message" severity level; matches exactly. assert (condition) then report "message" severity level; has incorrect 'then'. assert condition, "message", severity level; uses commas incorrectly. assert condition report "message" severity level misses the semicolon.

3. Final Answer:

   assert condition report "message" severity level; -> Option C

4. Quick Check:

   Correct assert syntax ends with semicolon [OK]

Hint: Remember assert ends with semicolon and uses 'report' keyword [OK]

Common Mistakes:

• Omitting semicolon at the end
• Using commas instead of keywords
• Adding 'then' after condition

3. What will be the output during simulation for the following VHDL code snippet?

signal x : integer := 5;
begin
  assert x > 10 report "Value too low" severity warning;
end;

medium

A. Simulation stops with error

B. Warning message: "Value too low" is displayed

C. No message is displayed, simulation continues silently

D. Syntax error due to missing semicolon

Solution

1. Step 1: Evaluate the assert condition

   The condition x > 10 is false since x = 5.

2. Step 2: Understand severity level effect

   Severity is warning, so simulation shows a warning message but continues.

3. Final Answer:

   Warning message: "Value too low" is displayed -> Option B

4. Quick Check:

   False condition + warning severity = warning message [OK]

Hint: False assert with warning shows message but continues [OK]

Common Mistakes:

• Thinking simulation stops on warning severity
• Ignoring the severity level
• Assuming no message if condition false

4. Identify the error in this VHDL assert statement:

assert (a = b) report "Mismatch" severity error

medium

A. Missing semicolon at the end

B. Incorrect use of parentheses around condition

C. Wrong severity level keyword

D. Missing report keyword

Solution

1. Step 1: Check syntax completeness

   The assert statement must end with a semicolon; it is missing here.

2. Step 2: Verify other parts

   Parentheses around condition are allowed, severity keyword is correct, and report keyword is present.

3. Final Answer:

   Missing semicolon at the end -> Option A

4. Quick Check:

   Assert statements end with semicolon [OK]

Hint: Always end assert statements with semicolon [OK]

Common Mistakes:

• Forgetting semicolon
• Thinking parentheses are not allowed
• Confusing severity keywords

5. You want to verify that a signal data_valid is always true during simulation. Which assert statement correctly stops simulation on failure and shows an error message?

hard

A. assert data_valid report "Data invalid" severity critical;

B. assert data_valid report "Data invalid" severity warning;

C. assert not data_valid report "Data invalid" severity note;

D. assert data_valid report "Data invalid" severity error;

Solution

1. Step 1: Understand severity levels for stopping simulation

   Severity error stops simulation and reports an error message.

2. Step 2: Analyze each option

   assert data_valid report "Data invalid" severity warning; uses warning (does not stop). assert data_valid report "Data invalid" severity error; uses error (correct). assert not data_valid report "Data invalid" severity note; negates condition and uses note (no stop). assert data_valid report "Data invalid" severity critical; uses critical which is not a valid severity.

3. Final Answer:

   assert data_valid report "Data invalid" severity error; -> Option D

4. Quick Check:

   Error severity stops simulation = assert data_valid report "Data invalid" severity error; [OK]

Hint: Use severity error to stop simulation on assert failure [OK]

Common Mistakes:

• Using warning instead of error severity
• Negating condition incorrectly
• Using invalid severity keywords