Assert statement for verification in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to assert that signal 'clk' is '1'.

VHDL

assert clk = [1] report "Clock is not high" severity error;

Drag options to blanks, or click blank then click option'

Atrue

B'0'

C1

D'1'

Attempts:

3 left

💡 Hint

Common Mistakes

Using double quotes instead of single quotes for bit values.

Using 1 without quotes which is invalid for std_logic.

The assert statement checks if the signal 'clk' equals '1' (logic high).

2fill in blank

medium

Complete the code to assert that 'data_ready' is true.

VHDL

assert [1] report "Data not ready" severity warning;

Drag options to blanks, or click blank then click option'

Adata_ready = true

Bdata_ready = '0'

Cdata_ready = '1'

Ddata_ready

Attempts:

3 left

💡 Hint

Common Mistakes

Using true without quotes for std_logic signals.

Checking for '0' instead of '1'.

The assert checks if 'data_ready' signal equals '1' (true in std_logic).

3fill in blank

hard

Fix the error in the assert statement to check if 'reset' is low.

VHDL

assert reset = [1] report "Reset not low" severity error;

Drag options to blanks, or click blank then click option'

A'0'

B'1'

C0

Dfalse

Attempts:

3 left

💡 Hint

Common Mistakes

Using 0 without quotes which is invalid.

Using '1' instead of '0' for low.

The reset signal is low when it equals '0' in std_logic.

4fill in blank

hard

Fill both blanks to assert that 'enable' is high and report a custom message.

VHDL

assert [1] report [2] severity note;

Drag options to blanks, or click blank then click option'

Aenable = '1'

B"Enable signal low"

C"Enable signal high"

Denable = '0'

Attempts:

3 left

💡 Hint

Common Mistakes

Swapping the message and condition.

Using single quotes for the message.

The assert checks if 'enable' is '1' and reports "Enable signal high" if false.

5fill in blank

hard

Fill all three blanks to assert 'valid' is '1', report 'Invalid data', and set severity to error.

VHDL

assert [1] report [2] severity [3];

Drag options to blanks, or click blank then click option'

Avalid = '1'

B"Invalid data"

Cerror

Dwarning

Attempts:

3 left

💡 Hint

Common Mistakes

Using severity 'warning' instead of 'error'.

Not quoting the message string.

The assert checks if 'valid' is '1', reports "Invalid data" if false, and sets severity to error.

Practice

1. What is the main purpose of the assert statement in VHDL?

easy

A. To check conditions during simulation and report errors

B. To declare variables in the design

C. To assign values to signals

D. To create loops in the code

Solution

1. Step 1: Understand the role of assert in VHDL

   The assert statement is used to verify conditions during simulation, helping catch errors early.

2. Step 2: Compare with other options

   Other options describe unrelated tasks: declaring variables, assigning signals, or looping.

3. Final Answer:

   To check conditions during simulation and report errors -> Option A

4. Quick Check:

   Assert checks conditions = To check conditions during simulation and report errors [OK]

Hint: Assert is for checking conditions during simulation [OK]

Common Mistakes:

• Confusing assert with signal assignment
• Thinking assert declares variables
• Assuming assert creates loops

2. Which of the following is the correct syntax for an assert statement in VHDL?

easy

A. assert condition, "message", severity level;

B. assert (condition) then report "message" severity level;

C. assert condition report "message" severity level;

D. assert condition report "message" severity level

Solution

1. Step 1: Recall correct assert syntax

   The correct syntax is: assert condition report "message" severity level; with a semicolon at the end.

2. Step 2: Check each option

   assert condition report "message" severity level; matches exactly. assert (condition) then report "message" severity level; has incorrect 'then'. assert condition, "message", severity level; uses commas incorrectly. assert condition report "message" severity level misses the semicolon.

3. Final Answer:

   assert condition report "message" severity level; -> Option C

4. Quick Check:

   Correct assert syntax ends with semicolon [OK]

Hint: Remember assert ends with semicolon and uses 'report' keyword [OK]

Common Mistakes:

• Omitting semicolon at the end
• Using commas instead of keywords
• Adding 'then' after condition

3. What will be the output during simulation for the following VHDL code snippet?

signal x : integer := 5;
begin
  assert x > 10 report "Value too low" severity warning;
end;

medium

A. Simulation stops with error

B. Warning message: "Value too low" is displayed

C. No message is displayed, simulation continues silently

D. Syntax error due to missing semicolon

Solution

1. Step 1: Evaluate the assert condition

   The condition x > 10 is false since x = 5.

2. Step 2: Understand severity level effect

   Severity is warning, so simulation shows a warning message but continues.

3. Final Answer:

   Warning message: "Value too low" is displayed -> Option B

4. Quick Check:

   False condition + warning severity = warning message [OK]

Hint: False assert with warning shows message but continues [OK]

Common Mistakes:

• Thinking simulation stops on warning severity
• Ignoring the severity level
• Assuming no message if condition false

4. Identify the error in this VHDL assert statement:

assert (a = b) report "Mismatch" severity error

medium

A. Missing semicolon at the end

B. Incorrect use of parentheses around condition

C. Wrong severity level keyword

D. Missing report keyword

Solution

1. Step 1: Check syntax completeness

   The assert statement must end with a semicolon; it is missing here.

2. Step 2: Verify other parts

   Parentheses around condition are allowed, severity keyword is correct, and report keyword is present.

3. Final Answer:

   Missing semicolon at the end -> Option A

4. Quick Check:

   Assert statements end with semicolon [OK]

Hint: Always end assert statements with semicolon [OK]

Common Mistakes:

• Forgetting semicolon
• Thinking parentheses are not allowed
• Confusing severity keywords

5. You want to verify that a signal data_valid is always true during simulation. Which assert statement correctly stops simulation on failure and shows an error message?

hard

A. assert data_valid report "Data invalid" severity critical;

B. assert data_valid report "Data invalid" severity warning;

C. assert not data_valid report "Data invalid" severity note;

D. assert data_valid report "Data invalid" severity error;

Solution

1. Step 1: Understand severity levels for stopping simulation

   Severity error stops simulation and reports an error message.

2. Step 2: Analyze each option

   assert data_valid report "Data invalid" severity warning; uses warning (does not stop). assert data_valid report "Data invalid" severity error; uses error (correct). assert not data_valid report "Data invalid" severity note; negates condition and uses note (no stop). assert data_valid report "Data invalid" severity critical; uses critical which is not a valid severity.

3. Final Answer:

   assert data_valid report "Data invalid" severity error; -> Option D

4. Quick Check:

   Error severity stops simulation = assert data_valid report "Data invalid" severity error; [OK]

Hint: Use severity error to stop simulation on assert failure [OK]

Common Mistakes:

• Using warning instead of error severity
• Negating condition incorrectly
• Using invalid severity keywords