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VHDLprogramming~10 mins

Assert statement for verification in VHDL - Interactive Code Practice

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Practice - 5 Tasks
Answer the questions below
1fill in blank
easy

Complete the code to assert that signal 'clk' is '1'.

VHDL
assert clk = [1] report "Clock is not high" severity error;
Drag options to blanks, or click blank then click option'
Atrue
B'0'
C1
D'1'
Attempts:
3 left
💡 Hint
Common Mistakes
Using double quotes instead of single quotes for bit values.
Using 1 without quotes which is invalid for std_logic.
2fill in blank
medium

Complete the code to assert that 'data_ready' is true.

VHDL
assert [1] report "Data not ready" severity warning;
Drag options to blanks, or click blank then click option'
Adata_ready = true
Bdata_ready = '0'
Cdata_ready = '1'
Ddata_ready
Attempts:
3 left
💡 Hint
Common Mistakes
Using true without quotes for std_logic signals.
Checking for '0' instead of '1'.
3fill in blank
hard

Fix the error in the assert statement to check if 'reset' is low.

VHDL
assert reset = [1] report "Reset not low" severity error;
Drag options to blanks, or click blank then click option'
A'0'
B'1'
C0
Dfalse
Attempts:
3 left
💡 Hint
Common Mistakes
Using 0 without quotes which is invalid.
Using '1' instead of '0' for low.
4fill in blank
hard

Fill both blanks to assert that 'enable' is high and report a custom message.

VHDL
assert [1] report [2] severity note;
Drag options to blanks, or click blank then click option'
Aenable = '1'
B"Enable signal low"
C"Enable signal high"
Denable = '0'
Attempts:
3 left
💡 Hint
Common Mistakes
Swapping the message and condition.
Using single quotes for the message.
5fill in blank
hard

Fill all three blanks to assert 'valid' is '1', report 'Invalid data', and set severity to error.

VHDL
assert [1] report [2] severity [3];
Drag options to blanks, or click blank then click option'
Avalid = '1'
B"Invalid data"
Cerror
Dwarning
Attempts:
3 left
💡 Hint
Common Mistakes
Using severity 'warning' instead of 'error'.
Not quoting the message string.