Assert statement for verification in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of Assert Statement in VHDL Simulation

What will be the output message when this VHDL code runs in simulation?

VHDL

architecture Behavioral of test is
  signal a : integer := 5;
begin
  process
  begin
    assert a = 10
    report "Value of a is not 10!"
    severity warning;
    wait;
  end process;
end Behavioral;

A Warning: Value of a is not 10!

B Error: Value of a is not 10!

C No message, assertion passes silently

D Simulation stops with failure

💡 Hint

Check the severity level used in the assert statement.

The assert condition fails because 'a' is 5, not 10. The severity is 'warning', so the simulator prints a warning message but continues.

🧠 Conceptual

intermediate

Purpose of Assert Statement in VHDL

What is the main purpose of using an assert statement in VHDL verification?

A To assign values to signals during synthesis

B To check conditions during simulation and report errors or warnings

C To declare variables inside a process

D To optimize the hardware implementation

💡 Hint

Think about what assert does during simulation.

Assert statements verify conditions during simulation and help catch design errors by reporting messages with different severity levels.

🔧 Debug

advanced

Identify the Error in Assert Statement Syntax

Which option contains the correct syntax for an assert statement in VHDL?

VHDL

assert (x > 0) report "x must be positive" severity error;

A assert x > 0 report "x must be positive" severity error;

B assert x > 0, report "x must be positive" severity error;

C assert (x > 0) report "x must be positive" severity error;

D assert (x > 0) then report "x must be positive" severity error;

💡 Hint

Check the placement of parentheses and keywords.

The correct syntax requires the condition in parentheses, followed by 'report' and 'severity' keywords without commas or 'then'.

❓ Predict Output

advanced

Effect of Severity Level in Assert Statement

What happens when this VHDL assert statement triggers during simulation?

VHDL

assert false
report "Critical failure detected"
severity failure;

A Simulation prints the message and stops immediately

B Simulation prints a warning but does not stop

C Simulation ignores the assert and continues silently

D Simulation prints the message and continues

💡 Hint

Severity 'failure' has a special meaning in simulation.

Severity 'failure' causes the simulator to print the message and stop the simulation immediately.

🚀 Application

expert

Count Assert Messages During Simulation

Given this VHDL process, how many assert messages will be reported during simulation?

VHDL

process
  variable count : integer := 0;
begin
  for i in 1 to 5 loop
    assert i mod 2 = 0
    report "Odd number found: " & integer'image(i)
    severity warning;
    count := count + 1;
  end loop;
  wait;
end process;

A 0

B 2

C 5

D 3

💡 Hint

Count how many numbers from 1 to 5 are odd.

The assert triggers when i mod 2 != 0, i.e., for odd numbers 1, 3, 5, so 3 messages are reported.