Assert statement for verification in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of Assert Statement in VHDL Simulation

What will be the output message when this VHDL code runs in simulation?

VHDL

architecture Behavioral of test is
  signal a : integer := 5;
begin
  process
  begin
    assert a = 10
    report "Value of a is not 10!"
    severity warning;
    wait;
  end process;
end Behavioral;

A Warning: Value of a is not 10!

B Error: Value of a is not 10!

C No message, assertion passes silently

D Simulation stops with failure

💡 Hint

Check the severity level used in the assert statement.

The assert condition fails because 'a' is 5, not 10. The severity is 'warning', so the simulator prints a warning message but continues.

🧠 Conceptual

intermediate

Purpose of Assert Statement in VHDL

What is the main purpose of using an assert statement in VHDL verification?

A To assign values to signals during synthesis

B To check conditions during simulation and report errors or warnings

C To declare variables inside a process

D To optimize the hardware implementation

💡 Hint

Think about what assert does during simulation.

Assert statements verify conditions during simulation and help catch design errors by reporting messages with different severity levels.

🔧 Debug

advanced

Identify the Error in Assert Statement Syntax

Which option contains the correct syntax for an assert statement in VHDL?

VHDL

assert (x > 0) report "x must be positive" severity error;

A assert x > 0 report "x must be positive" severity error;

B assert x > 0, report "x must be positive" severity error;

C assert (x > 0) report "x must be positive" severity error;

D assert (x > 0) then report "x must be positive" severity error;

💡 Hint

Check the placement of parentheses and keywords.

The correct syntax requires the condition in parentheses, followed by 'report' and 'severity' keywords without commas or 'then'.

❓ Predict Output

advanced

Effect of Severity Level in Assert Statement

What happens when this VHDL assert statement triggers during simulation?

VHDL

assert false
report "Critical failure detected"
severity failure;

A Simulation prints the message and stops immediately

B Simulation prints a warning but does not stop

C Simulation ignores the assert and continues silently

D Simulation prints the message and continues

💡 Hint

Severity 'failure' has a special meaning in simulation.

Severity 'failure' causes the simulator to print the message and stop the simulation immediately.

🚀 Application

expert

Count Assert Messages During Simulation

Given this VHDL process, how many assert messages will be reported during simulation?

VHDL

process
  variable count : integer := 0;
begin
  for i in 1 to 5 loop
    assert i mod 2 = 0
    report "Odd number found: " & integer'image(i)
    severity warning;
    count := count + 1;
  end loop;
  wait;
end process;

A 0

B 2

C 5

D 3

💡 Hint

Count how many numbers from 1 to 5 are odd.

The assert triggers when i mod 2 != 0, i.e., for odd numbers 1, 3, 5, so 3 messages are reported.

Practice

1. What is the main purpose of the assert statement in VHDL?

easy

A. To check conditions during simulation and report errors

B. To declare variables in the design

C. To assign values to signals

D. To create loops in the code

Solution

1. Step 1: Understand the role of assert in VHDL

   The assert statement is used to verify conditions during simulation, helping catch errors early.

2. Step 2: Compare with other options

   Other options describe unrelated tasks: declaring variables, assigning signals, or looping.

3. Final Answer:

   To check conditions during simulation and report errors -> Option A

4. Quick Check:

   Assert checks conditions = To check conditions during simulation and report errors [OK]

Hint: Assert is for checking conditions during simulation [OK]

Common Mistakes:

• Confusing assert with signal assignment
• Thinking assert declares variables
• Assuming assert creates loops

2. Which of the following is the correct syntax for an assert statement in VHDL?

easy

A. assert condition, "message", severity level;

B. assert (condition) then report "message" severity level;

C. assert condition report "message" severity level;

D. assert condition report "message" severity level

Solution

1. Step 1: Recall correct assert syntax

   The correct syntax is: assert condition report "message" severity level; with a semicolon at the end.

2. Step 2: Check each option

   assert condition report "message" severity level; matches exactly. assert (condition) then report "message" severity level; has incorrect 'then'. assert condition, "message", severity level; uses commas incorrectly. assert condition report "message" severity level misses the semicolon.

3. Final Answer:

   assert condition report "message" severity level; -> Option C

4. Quick Check:

   Correct assert syntax ends with semicolon [OK]

Hint: Remember assert ends with semicolon and uses 'report' keyword [OK]

Common Mistakes:

• Omitting semicolon at the end
• Using commas instead of keywords
• Adding 'then' after condition

3. What will be the output during simulation for the following VHDL code snippet?

signal x : integer := 5;
begin
  assert x > 10 report "Value too low" severity warning;
end;

medium

A. Simulation stops with error

B. Warning message: "Value too low" is displayed

C. No message is displayed, simulation continues silently

D. Syntax error due to missing semicolon

Solution

1. Step 1: Evaluate the assert condition

   The condition x > 10 is false since x = 5.

2. Step 2: Understand severity level effect

   Severity is warning, so simulation shows a warning message but continues.

3. Final Answer:

   Warning message: "Value too low" is displayed -> Option B

4. Quick Check:

   False condition + warning severity = warning message [OK]

Hint: False assert with warning shows message but continues [OK]

Common Mistakes:

• Thinking simulation stops on warning severity
• Ignoring the severity level
• Assuming no message if condition false

4. Identify the error in this VHDL assert statement:

assert (a = b) report "Mismatch" severity error

medium

A. Missing semicolon at the end

B. Incorrect use of parentheses around condition

C. Wrong severity level keyword

D. Missing report keyword

Solution

1. Step 1: Check syntax completeness

   The assert statement must end with a semicolon; it is missing here.

2. Step 2: Verify other parts

   Parentheses around condition are allowed, severity keyword is correct, and report keyword is present.

3. Final Answer:

   Missing semicolon at the end -> Option A

4. Quick Check:

   Assert statements end with semicolon [OK]

Hint: Always end assert statements with semicolon [OK]

Common Mistakes:

• Forgetting semicolon
• Thinking parentheses are not allowed
• Confusing severity keywords

5. You want to verify that a signal data_valid is always true during simulation. Which assert statement correctly stops simulation on failure and shows an error message?

hard

A. assert data_valid report "Data invalid" severity critical;

B. assert data_valid report "Data invalid" severity warning;

C. assert not data_valid report "Data invalid" severity note;

D. assert data_valid report "Data invalid" severity error;

Solution

1. Step 1: Understand severity levels for stopping simulation

   Severity error stops simulation and reports an error message.

2. Step 2: Analyze each option

   assert data_valid report "Data invalid" severity warning; uses warning (does not stop). assert data_valid report "Data invalid" severity error; uses error (correct). assert not data_valid report "Data invalid" severity note; negates condition and uses note (no stop). assert data_valid report "Data invalid" severity critical; uses critical which is not a valid severity.

3. Final Answer:

   assert data_valid report "Data invalid" severity error; -> Option D

4. Quick Check:

   Error severity stops simulation = assert data_valid report "Data invalid" severity error; [OK]

Hint: Use severity error to stop simulation on assert failure [OK]

Common Mistakes:

• Using warning instead of error severity
• Negating condition incorrectly
• Using invalid severity keywords